# US 11,121,677 B1 · Transconductance amplifier based on self-biased cascode structure

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- Number: US 11,121,677 B1
- Document ID: US11121677B1
- Status: Granted
- Kind: B1
- Application number: 16/625,671
- Filed: 2016-01-26
- Published: 2021-09-30
- Granted: 2021-09-14
- Earliest claimed: 2016-01-21
- Assignees: China Electronic Technology Corporation, 24Th Research Institute
- Applicants: China Electronic Technology Corporation, 24Th Research Institute
- Inventors: Daiguo Xu; Gangyi Hu; Ruzhang Li; Jian'an Wang; Guangbing Chen; Yuxin Wang; Tao Liu; Lu Liu; Minming Deng; Hanfu Shi; Xu Wang
- Web page: https://patentgrep.com/patent/US11121677B1

## CPC

- H03F 1/223: {with MOSFET's}
- H03F 3/45183: {Long tailed pairs (H03F3/4521, H03F3/45237 take precedence)}
- H03F 2200/411: the output amplifying stage of an amplifier comprising two power stages
- H03G 1/00: Details of arrangements for controlling amplification
- H03F: AMPLIFIERS
- H03G: CONTROL OF AMPLIFICATION

## Abstract

Provided in the present invention is a transconductance amplifier based on a self-biased cascode structure. The transconductance amplifier includes a self-biased cascode input-stage structure constituted by PMOS (P-channel Metal Oxide Semiconductor) input transistors M1, M2, M3 and M4, a self-biased cascode first-stage load structure constituted by NMOS (N-channel Metal Oxide Semiconductor) transistors M5, M6, M7 and M8, a second-stage common-source amplifier structure constituted by an NMOS transistor M9 and a PMOS transistor M10, a bias circuit structure constituted by NMOS transistors M11 and M12 and a PMOS transistor M13, an amplifier compensation capacitor Cc, an amplifier load capacitor CL, a reference current source Iref and a PMOS transistor M0 that provides a constant current source function. Further provided in the present invention is a transconductance amplifier based on a self-biased cascode structure, which adopts an NMOS transistor as an input transistor. Both input transistors and load transistors of a first-stage amplifier of the present invention adopt self-biased cascode structures, such that the output impedance and the DC gain of the first-stage amplifier are increased. Substrate voltages of the MOS transistors of the first-stage amplifier are provided by an amplifier bias circuit. Owing to a connection mode of the compensation capacitor Cc, a higher figure of merit is achieved.

## Claims

### Claim 1

A transconductance amplifier based on a self-biased cascode structure, comprising a self-biased cascode input-stage structure constituted by PMOS (P-channel Metal Oxide Semiconductor) input transistors M1, M2, M3 and M4, a self-biased cascode first-stage load structure constituted by NMOS (N-channel Metal Oxide Semiconductor) transistors M5, M6, M7 and M8, a second-stage common-source amplifier structure constituted by an NMOS transistor M9 and a PMOS transistor M10, a bias circuit structure constituted by NMOS transistors M11 and M12 and a PMOS transistor M13, an amplifier compensation capacitor Cc, an amplifier load capacitor CL, a reference current source Iref and a PMOS transistor M0 that provides a constant current source function, wherein:
sources of the PMOS input transistors M1 and M2 are connected to a drain of the PMOS transistor M0; gates of the PMOS input transistors M1 and M3 are connected to an input signal VIN; gates of the PMOS input transistors M2 and M4 are connected to an input signal VIP; a drain of the PMOS input transistor M1 is connected to a source of the PMOS input transistor M3; a drain of the PMOS input transistor M2 is connected to a source of the PMOS input transistor M4; substrates of the PMOS input transistors M3 and M4 are connected to a bias voltage Vp; and the bias voltage Vp is provided by a gate voltage of the PMOS transistor M13 of which a gate and a drain are connected in an amplifier bias circuit;
a gate and a drain of the NMOS transistor M5 are both connected to gates of the NMOS transistors M6, M7 and M8 and a drain of the PMOS input transistor M3; a drain of the NMOS transistor M6 is connected to a drain of the PMOS input transistor M4; a source of the NMOS transistor M5 is connected to a drain of the NMOS transistor M7; a source of the NMOS transistor M6 is connected to a drain of the NMOS transistor M8; sources of the NMOS transistors M7 and M8 are grounded; substrates of the NMOS transistors M5 and M6 are connected to a bias voltage Vn; and the bias voltage Vn is provided by a gate voltage of the NMOS transistor M11 of which a gate and a drain are connected in the amplifier bias circuit;
sources of the PMOS transistors M10, M0 and M13 are connected to a supply voltage vdd; a gate of the PMOS transistor M10 is connected to gates of the PMOS transistors M0 and M13; a drain of the PMOS transistor M10, one end of the compensation capacitor Cc, a drain of the NMOS transistor M9 and one end of the load capacitor CL are connected to form a connection node; the connection node is an output end Vout of the transconductance amplifier; the other end of the compensation capacitor Cc is connected to a drain of the PMOS input transistor M2; the other end of the load capacitor CL and a source of the NMOS transistor M9 are grounded; and a gate of the NMOS transistor M9 is connected to a drain of the PMOS input transistor M4;
a drain of the PMOS transistor M13 is connected to a drain of the NMOS transistor M12; a gate of the NMOS transistor M12 is connected to one end of the reference current source Iref and a gate and a drain of the NMOS transistor M11; sources of the NMOS transistors M11 and M12 are grounded; and the other end of the reference current source Iref is connected to the supply voltage vdd.

### Claim 2 (depends on 1)

The transconductance amplifier based on the self-biased cascode structure according to claim 1, wherein a ratio of a channel length of the PMOS input transistor M1 to a channel length of the PMOS input transistor M3 is 1:4, and a ratio of a channel length of the NMOS transistor M5 to a channel length of the NMOS M7 is 1:4.

### Claim 3 (depends on 1)

The transconductance amplifier based on the self-biased cascode structure according to claim 1, wherein the compensation capacitor Cc has the capacitance of 2 pF to 4 pF.

### Claim 4

A transconductance amplifier based on a self-biased cascode structure, comprising a self-biased cascode input-stage structure constituted by NMOS input transistors M1, M2, M3 and M4, a self-biased cascode first-stage load structure constituted by PMOS transistors M5, M6, M7 and M8, a second-stage common-source amplifier structure constituted by an NMOS transistor M9 and a PMOS transistor M10, a bias circuit structure constituted by NMOS transistors M11 and M12 and a PMOS transistor M13, an amplifier compensation capacitor Cc, an amplifier load capacitor CL, a reference current source Iref and a PMOS transistor M0 that provides a constant current source function, wherein:
sources of the NMOS input transistors M1 and M2 are grounded; gates of the NMOS input transistors M1 and M3 are connected to an input signal VIN; gates of the NMOS input transistors M2 and M4 are connected to an input signal VIP; a drain of the NMOS input transistor M1 is connected to a source of the NMOS input transistor M3; a drain of the NMOS input transistor M2 is connected to a source of the NMOS input transistor M4; substrates of the NMOS input transistors M3 and M4 are connected to a bias voltage Vn; and the bias voltage Vn is provided by a gate voltage of the NMOS transistor M11 of which a gate and a drain are connected in an amplifier bias circuit;
a gate and a drain of the PMOS transistor M5 are both connected to gates of the PMOS transistors M6, M7 and M8 and a drain of the NMOS input transistor M3; a drain of the PMOS transistor M6 is connected to a drain of the NMOS input transistor M4; a source of the PMOS transistor M5 is connected to a drain of the PMOS transistor M7; a source of the PMOS transistor M6 is connected to a drain of the PMOS transistor M8; sources of the PMOS transistors M7 and M8 are connected to a drain of the PMOS transistor M0; substrates of the PMOS transistors M5 and M6 are connected to a bias voltage Vp; and the bias voltage Vp is provided by a gate voltage of the PMOS transistor M13 of which a gate and a drain are connected in the amplifier bias circuit;
a source of the PMOS transistor M10 is connected to a supply voltage vdd; a drain of the PMOS transistor M10, one end of the compensation capacitor Cc, a drain of the NMOS transistor M9 and one end of the load capacitor CL are connected to form a connection node; the connection node is an output end Vout of the transconductance amplifier; a gate of the PMOS transistor M10 is connected to a drain of the NMOS input transistor M4; the other end of the compensation capacitor Cc is connected to a drain of the PMOS input transistor M2; the other end of the load capacitor CL and a source of the NMOS transistor M9 are grounded; and a gate of the NMOS transistor M9 is connected to a gate of the NMOS transistor M12; and
sources of the PMOS transistors M0 and M13 are connected to the supply voltage vdd; a gate of the PMOS transistor M0 is connected to a gate and a drain of the PMOS transistor M13; a drain of the PMOS transistor M13 is connected to a drain of the NMOS transistor M12; a gate of the NMOS transistor M12 is connected to one end of the reference current source Iref and a gate and a drain of the NMOS transistor M11; sources of the NMOS transistors M11 and M12 are grounded; and the other end of the reference current source Iref is connected to the supply voltage vdd.

### Claim 5 (depends on 4)

The transconductance amplifier based on the self-biased cascode structure according to claim 4, wherein a ratio of a channel length of the NMOS input transistor M1 to a channel length of the NMOS input transistor M3 is 1:4, and a ratio of a channel length of the PMOS transistor M5 to a channel length of the PMOS M7 is 1:4.

### Claim 6 (depends on 4)

The transconductance amplifier based on the self-biased cascode structure according to claim 4, wherein the compensation capacitor Cc has the capacitance of 2 pF to 4 pF.