# US 11,121,222 B2 · Semiconductor devices with graded dopant regions > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,121,222 B2 - Document ID: US11121222B2 - Status: Granted - Kind: B2 - Application number: 16/947,294 - Filed: 2020-07-27 - Published: 2021-01-07 - Granted: 2021-09-14 - Earliest claimed: 2004-09-03 - Assignees: Greenthread, LLC - Applicants: Greenthread, LLC - Inventors: G.R. Mohan Rao - Web page: https://patentgrep.com/patent/US11121222B2 ## CPC - H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)} - H10B 41/30: characterised by the memory core region - H10B 41/35: with a cell select transistor, e.g. NAND - H10D 12/441: {Vertical IGBTs} - H10D 62/60: Impurity distributions or concentrations - H10F 39/18: Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors - H10B 12/01: {Manufacture or treatment} - H10D 89/211: {Design considerations for internal polarisation (integrated injection logic H10D84/65)} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10B: ELECTRONIC MEMORY DEVICES - H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION ## Abstract Most semiconductor devices manufactured today, have uniform dopant concentration, either in the lateral or vertical device active (and isolation) regions. By grading the dopant concentration, the performance in various semiconductor devices can be significantly improved. Performance improvements can be obtained in application specific areas like increase in frequency of operation for digital logic, various power MOSFET and IGBT ICs, improvement in refresh time for DRAMs, decrease in programming time for nonvolatile memory, better visual quality including pixel resolution and color sensitivity for imaging ICs, better sensitivity for varactors in tunable filters, higher drive capabilities for JFETs, and a host of other applications. ## Claims ### Claim 1 A VLSI semiconductor device, comprising: a substrate of a first doping type at a first doping level having a surface; a first active region disposed adjacent the surface with a second doping type opposite in conductivity to the first doping type and within which transistors can be formed; a second active region separate from the first active region disposed adjacent to the first active region and within which transistors can be formed; transistors formed in at least one of the first active region or second active region; at least a portion of at least one of the first and second active regions having at least one graded dopant concentration to aid carrier movement from the first and second active regions towards an area of the substrate where there are no active regions; and at least one well region adjacent to the first or second active region containing at least one graded dopant region, the graded dopant region to aid carrier movement from the surface towards the area of the substrate where there are no active regions, wherein at least some of the transistors form digital logic of the VLSI semiconductor device. ### Claim 2 (depends on 1) The VLSI semiconductor device of claim 1, wherein the substrate is a p-type substrate. ### Claim 3 (depends on 1) The VLSI semiconductor device of claim 1, wherein the substrate has epitaxial silicon on top of a nonepitaxial substrate. ### Claim 4 (depends on 1) The VLSI semiconductor device of claim 1, wherein the first active region and second active region contain digital logic formed by one of either p-channel and n-channel devices. ### Claim 5 (depends on 1) The VLSI semiconductor device of claim 1, wherein the first active region and second active region contain either p-channel or n-channel devices in n−wells or p−wells, respectively, and each well has at least one graded dopant. ### Claim 6 (depends on 1) The VLSI semiconductor device of claim 1, wherein the first active region and second active region are each separated by at least one isolation region. ### Claim 7 (depends on 1) The VLSI semiconductor device of claim 1, wherein the graded dopant is fabricated with an ion implantation process. ### Claim 8 (depends on 1) The VLSI semiconductor device of claim 1, wherein the first and second active regions are formed adjacent the first surface of the substrate. ### Claim 9 (depends on 1) The VLSI semiconductor device of claim 1, wherein dopants of the graded dopant concentration in the first active region or the second active region are either p-type or n-type. ### Claim 10 (depends on 1) The VLSI semiconductor device of claim 1, wherein dopants of the graded dopant concentration in the first active region are both p-type and n-type. ### Claim 11 (depends on 1) The VLSI semiconductor device of claim 1, wherein dopants of the graded dopant concentration in the second active region are both p-type and n-type. ### Claim 12 (depends on 1) The VLSI semiconductor device of claim 1, wherein dopants of the graded dopant region in the well region are both p-type and n-type. ### Claim 13 (depends on 1) The VLSI semiconductor device of claim 1, wherein the transistors which can be formed in the first and second active regions are CMOS digital logic transistors requiring at least a source, a drain, a gate and a channel. ### Claim 14 (depends on 1) The VLSI semiconductor device of claim 1, wherein the device is a dynamic random access memory (DRAM). ### Claim 15 (depends on 1) The VLSI semiconductor device of claim 1, wherein the device is a complementary metal oxide semiconductor (CMOS) with a nonepitaxial substrate. ### Claim 16 (depends on 1) The VLSI semiconductor device of claim 1, wherein the device is a flash memory. ### Claim 17 (depends on 1) The VLSI semiconductor device of claim 1, wherein the device comprises digital logic and capacitors. ### Claim 18 (depends on 1) The VLSI semiconductor device of claim 1, wherein the device is central processing unit. ### Claim 19 (depends on 1) The VLSI semiconductor device of claim 1, wherein the device is an image sensor. ### Claim 20 (depends on 1) The VLSI semiconductor device of claim 1, wherein each of the first and second active regions are in the lateral or vertical direction. ### Claim 21 A VLSI semiconductor device, comprising: a substrate of a first doping type at a first doping level having a surface; a first active region disposed adjacent the surface of the substrate with a second doping type opposite in conductivity to the first doping type and within which transistors can be formed in the surface thereof; a second active region separate from the first active region disposed adjacent to the first active region and within which transistors can be formed in the surface thereof; transistors formed in at least one of the first active region or second active region; at least a portion of at least one of the first and second active regions having at least one graded dopant concentration to aid carrier movement from the surface to an area of the substrate where there are no active regions; and at least one well region adjacent to the first or second active region containing at least one graded dopant region, the graded dopant region to aid carrier movement from the surface to the area of the substrate where there are no active regions, and wherein the graded dopant concentration is linear, quasilinear, error function, complementary error function, or any combination thereof. ### Claim 22 (depends on 21) The VLSI semiconductor device of claim 21, wherein the substrate is an n-type substrate. ### Claim 23 (depends on 21) The VLSI semiconductor device of claim 21, wherein the substrate is a p-type substrate. ### Claim 24 (depends on 21) The VLSI semiconductor device of claim 21, wherein the substrate has epitaxial silicon on top of a nonepitaxial substrate. ### Claim 25 (depends on 21) The VLSI semiconductor device of claim 21, wherein the first active region and second active region contain at least one of either p-channel and n-channel devices. ### Claim 26 (depends on 21) The VLSI semiconductor device of claim 21, wherein the first active region and second active region contain either p-channel or n-channel devices in n−wells or p−wells, respectively, and each well has at least one graded dopant. ### Claim 27 (depends on 21) The VLSI semiconductor device of claim 21, wherein the first active region and second active region are each separated by at least one isolation region. ### Claim 28 (depends on 21) The VLSI semiconductor device of claim 21, wherein dopants of the graded dopant concentration in the first active region or the second active region are either p-type or n-type. ### Claim 29 (depends on 21) The VLSI semiconductor device of claim 21, wherein dopants of the graded dopant concentration in the first active region are both p-type and n-type. ### Claim 30 (depends on 21) The VLSI semiconductor device of claim 21, wherein dopants of the graded dopant concentration in the second active region are both p-type and n-type. ### Claim 31 (depends on 21) The VLSI semiconductor device of claim 21, wherein dopants of the graded dopant region in the well region are both p-type and n-type. ### Claim 32 (depends on 21) The VLSI semiconductor device of claim 21, wherein the graded dopant is fabricated with an ion implantation process. ### Claim 33 (depends on 21) The VLSI semiconductor device of claim 21, wherein the substrate is a complementary metal oxide semiconductor (CMOS) device. ### Claim 34 (depends on 21) The VLSI semiconductor device of claim 21, wherein the device is a flash memory. ### Claim 35 (depends on 21) The VLSI semiconductor device of claim 21, wherein the device is a logic device with capacitors in at least some of the first or second active regions. ### Claim 36 (depends on 21) The VLSI semiconductor device of claim 21, wherein the device is central processing unit. ### Claim 37 (depends on 21) The VLSI semiconductor device of claim 21, wherein the device is an image sensor. ### Claim 38 (depends on 21) The VLSI semiconductor device of claim 21, wherein each of the first and second active regions are in the lateral or vertical direction. ### Claim 39 A semiconductor device, comprising: a substrate of a first doping type at a first doping level; a first active region disposed adjacent to a surface of the substrate with a second doping type opposite in conductivity to the first doping type and within which transistors can be formed; a second active region separate from the first active region disposed adjacent to the first active region and within which transistors can be formed; transistors formed in at least one of the first active region or second active region; and at least a portion of at least one of the first and second active regions having at least one graded dopant concentration to aid carrier movement from the first or second active region to at least one substrate area where there is no active region. ### Claim 40 (depends on 39) The semiconductor device of claim 39 further comprising at least one well region adjacent to the first or second active region and containing at least one graded dopant region, the graded dopant region to aid carrier movement from any region in the well to the substrate area where there is no well. ### Claim 41 A semiconductor device, comprising: a substrate of a first doping type at a first doping level; a first active region disposed adjacent to a surface of the substrate with a second doping type opposite in conductivity to the first doping type and within which transistors can be formed; a second active region separate from the first active region disposed adjacent to the first active region and within which transistors can be formed; transistors formed in at least one of the first active region or second active region; and at least a portion of at least one of the first and second active regions having at least one graded dopant acceptor concentration to aid carrier movement from the first or second active region to at least one substrate area where there is no active region. ### Claim 42 A semiconductor device, comprising: a substrate of a first doping type at a first doping level; a first active region disposed adjacent to a surface of the substrate with a second doping type opposite in conductivity to the first doping type and within which transistors can be formed; a second active region separate from the first active region disposed adjacent to the first active region and within which transistors can be formed; transistors formed in at least one of the first active region or second active region; and at least a portion of at least one of the first and second active regions having at least one graded donor dopant concentration to aid carrier movement from the first or second active region to at least one substrate area where there is no active region. ### Claim 43 A semiconductor device, comprising: a substrate of a first doping type at a first doping level; a first active region disposed adjacent to a surface of the substrate with a second doping type opposite in conductivity to the first doping type and within which transistors can be formed; a second active region separate from the first active region disposed adjacent to the first active region and within which transistors can be formed; transistors formed in at least one of the first active region or second active region; and at least a portion of at least one of the first and second active regions having at least one graded acceptor dopant concentration and one graded donor dopant concentration to aid carrier movement from the first or second active region to at least one substrate area where there is no active region. ### Claim 44 A CMOS Semiconductor device comprising: a surface layer; a substrate; an active region including a source and a drain, disposed on one surface of the surface layer; a single drift layer disposed between the other surface of the surface layer and the substrate, the drift layer having a graded concentration of dopants extending between the surface layer and the substrate, the drift layer further having a first static unidirectional electric drift field to aid the movement of carriers from the surface layer to an area of the substrate where there are no active regions; and at least one well region disposed in the single drift layer, the well region having a graded concentration of dopants and a second static unidirectional electric drift field to aid the movement of carriers from the surface layer to the area of the substrate where there are no active regions.