US 11,120,183 B2Granted

Computer product for making a semiconductor device

AssigneesTaiwan Semiconductor Manufacturing Company, Ltd., National Taiwan University

InventorsChi-Chuan Chuang, Yi-Hsiang Lai, Jie-Hong Chiang

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Abstract

A computer program product, including a non-transitory, computer-readable medium containing instructions therein which, when executed by at least one processor, cause the at least one processor to perform a performance analysis of a network of interconnected nodes, the nodes configured to perform corresponding logic functions. The performance analysis includes, for a pipeline node in the network, calculating a pre-charging finish time of the pipeline node based on an evaluation finish time of a fanout node of the pipeline node and an acknowledge output time parameter of the fanout node. The performance analysis further includes, for the pipeline node in the network, calculating a cycle time of the pipeline node based on the calculated pre-charging finish time and an evaluation finish time of a fanin node of the pipeline node.

Claims20

Dependent claims

A computer program product, comprising a non-transitory, computer-readable medium containing instructions therein which, when executed by at least one processor, cause the at least one processor to perform:

receiving of a logic netlist;
accessing of a cell library;
generation of a network of interconnected nodes to corresponding dual-rail modules based on a technology node, the received logic netlist and the cell library, wherein generating the network of interconnected nodes comprises:
identifying a non-critical node among the nodes in a pipeline of the network based on calculated cycle times of the nodes in the pipeline;
and
replacing the non-critical node with a replacement node from the cell library, the replacement node having a smaller area than the non-critical node, the replacement node having lower performance than the non-critical node;
estimation of time delays for each node in the network by performing an analysis of the network of interconnected nodes, wherein
the nodes are configured to perform corresponding logic functions, and the performance analysis comprises, for a pipeline node in the network:
calculating a pre-charging finish time of the pipeline node based on an evaluation finish time of a fanout node of the pipeline node and an acknowledge output time parameter of the fanout node, and
calculating a cycle time of the pipeline node based on the calculated pre-charging finish time and an evaluation finish time of a fanin node of the pipeline node;
and
optimization of the network based on a result of the estimated time delays.

9 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/700,984Filed 2 Dec 2019 · division
Priority: 20 Aug 2014
Published: US 2020/0104436 A12 Apr 2020
Granted: 14 Sep 2021
Term ends: Not estimatedThe source records don’t support an estimate.

Classification17 codes

G06F 30/327
Circuit design at the digital level: logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
G06F 30/33
Circuit design at the digital level: design verification, e.g. functional simulation or model checking
G06F 30/3312
Using simulation: timing analysis
G06F 30/3323
Design verification, e.g. functional simulation or model checking: using formal methods, e.g. equivalence checking or property checking

Family

Application14/464,366Parent of this division · filed 20 Aug 2014
Application15/399,808Parent of this division · filed 6 Jan 2017
US 2020/0104436 A1Pre-grant publication · published 2 Apr 2020
US 10,496,773 B2Parent of this division
US 9,576,094 B2Parent of this division
US 2016/0055270 A1Published application
US 2017/0116354 A1Published application
US 11,120,183 B2This patent

From the US filing history. Foreign family members aren’t listed.