Execution unit configured to evaluate functions using at least one multiplier circuit

An execution unit for a processor, the execution unit configured to receive from a computer readable instruction an op code defining a nature of the instruction and to access an operand defined by the instruction, wherein the op code defines that the instruction generates a logarithm of the operand, the operand being a number in floating point format, the execution unit comprising:

• a look up table having a plurality of entries;
• a preparatory circuit configured to determine an index value in dependence upon the operand and search the look up table using the index value to locate an entry of the plurality of entries comprising a first natural logarithm associated with the index value;
• and
• control circuitry configured to provide a first value determined in dependence upon the operand and a second value determined in dependence upon the operand as inputs to at least one multiplier circuit of the execution unit so as to evaluate one or more terms of a Taylor series expansion of a second natural logarithm,
• wherein the control circuitry is configured to provide the natural logarithm associated with the index value and the one or more terms of the Taylor series expansion as inputs to at least one addition circuit so as to generate a mantissa of the logarithm of the operand.