Multi-addend adder circuit for stochastic computing

A multi-addend adder circuit, comprising:

• a summation circuit, wherein a plurality of input ends of the summation circuit are respectively configured to receive a plurality of pieces of first bitstream data;
• an adder circuit, wherein a first input end of the adder circuit is coupled to an output end of the summation circuit, and a second input end of the adder circuit is coupled to an output end of a buffer circuit;
• a comparator circuit, wherein an input end of the comparator circuit is coupled to an output end of the adder circuit, and an output end of the comparator circuit is configured to output a adding result of the plurality of pieces of first bitstream data;
• a subtractor circuit, wherein a first input end of the subtractor circuit is coupled to the output end of the adder circuit, a second input end of the subtractor circuit is coupled to the output end of the comparator, and a output end of the subtractor circuit is coupled to the input end of the buffer circuit.

A multi-addend adder circuit, comprising:

• a buffer circuit, configured to:
• store buffer input data for one cycle and generate buffer output data, wherein
• when the buffer input data is 0, a value of the buffer output data remains unchanged;
• and
• when the buffer input data is 1, a value of the buffer output data is flipped;
• and
• a computing circuit, configured to:
• perform computing on a plurality of pieces of first bitstream data and the buffer output data that are input to the computing circuit, and output a plurality of pieces of second bitstream data and the buffer input data;
• wherein
• the buffer input data is a value obtained by performing an XOR operation on the plurality of pieces of first bitstream data, a quantity of the plurality of pieces of second bitstream data is a value obtained by rounding up a result of dividing a quantity of the plurality of pieces of first bitstream data by 2, and the plurality of pieces of second bitstream data comprise W1 pieces of bitstream data whose values are 1, Wt pieces of bitstream data that has a same value as the buffer output data, and W0 pieces of bitstream data whose values are 0;
• wherein W1 is a value obtained by rounding down a result of dividing summation data by 2, Wt is a remainder of dividing the summation data by 2, and W0 is a difference between the quantity of the plurality of pieces of second bitstream data and a sum of W1 and Wt, wherein the summation data in each cycle is a quantity of pieces of the first bitstream data whose values are 1 in the plurality of pieces of the first bitstream data in the cycle;
• and the plurality of pieces of first bitstream data and the plurality of pieces of second bitstream data are data in a polar representation, and the cycle is a cycle in which the plurality of pieces of first bitstream data are input.