# US 11,116,084 B2 · Method, device and system for providing etched metallization structures > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,116,084 B2 - Document ID: US11116084B2 - Status: Granted - Kind: B2 - Application number: 16/634,804 - Filed: 2017-09-27 - Published: 2020-07-23 - Granted: 2021-09-07 - Earliest claimed: 2017-09-27 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Jeremy Ecton; Nicholas Haehn; Oscar Ojeda; Arnab Roy; Timothy White; Suddhasattwa Nad; Hsin-Wei Wang - Web page: https://patentgrep.com/patent/US11116084B2 ## CPC - H10P 50/667: {by liquid etching only} - H05K 3/181: {by electroless plating (adhesives therefor H05K3/387)} - H05K 3/188: {by direct electroplating} - H05K 3/4644: {by building the multilayer layer by layer, i.e. build-up multilayer circuits (making via holes in the insulating layers H05K3/0011; special circuit boards as base or core whereon the multilayer is built H05K3/4602)} - H10W 20/0633: {using subtractive patterning of the conductive members} - H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) - H10W 70/66: Conductive materials thereof - H10W 70/685: comprising multiple insulating layers - H10P 14/47: Electrolytic deposition, i.e. electroplating; Electroless plating - H10W 20/063: {by forming conductive members before forming protective insulating material} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract Techniques and mechanisms for providing anisotropic etching of a metallization layer of a substrate. In an embodiment, the metallization layer includes grains of a conductor, wherein a first average grain size and a second average grain size correspond, respectively, to a first sub-layer and a second sub-layer of the metallization layer. The first sub-layer and the second sub-layer each span at least 5% of a thickness of the metallization layer. A difference between the first average grain size and the second average grain size is at least 10% of the first average grain size. In another embodiment, a first condition of metallization processing contributes to grains of the first sub-layer being relatively large, wherein an alternative condition of metallization processing contributes to grains of the second sub-layer being relatively small. A grain size gradient across a thickness of the metallization layer facilitates etching processes being anisotropic. ## Claims ### Claim 1 A circuit device comprising: a first layer comprising a dielectric; and a second layer of a metal on the first layer, the second layer comprising: a first sub-layer of the metal, the first sub-layer comprising a first average grain size, wherein the first sub-layer spans at least 5% of a thickness of the second layer; a second sub-layer of the metal, the second sub-layer comprising a second average, grain size wherein the second sub-layer of the metallization layer which spans at least 5% of the thickness of the metallization second layer, the second average grain size smaller than the first average grain size; and a third sub-layer of the metal, the third sub-layer comprising a third average grain size, wherein the third sub-layer spans at least 5% of the thickness of the second layer; wherein: a first difference between the first average grain size and the second average grain size is at least 10% of the first average grain size; and a second difference between the third average grain size and the second average grain size is at least 10% of the third average grain size. ### Claim 2 (depends on 1) The circuit device of claim 1, wherein a package substrate of the circuit device comprises the second layer. ### Claim 3 (depends on 2) The circuit device of claim 2, wherein a core of the package substrate comprises the second layer. ### Claim 4 (depends on 1) The circuit device of claim 1, wherein the first sub-layer adjoins the second sub-layer. ### Claim 5 (depends on 1) The circuit device of claim 1, wherein the first sub-layer is adjacent to a first side of the second layer. ### Claim 6 (depends on 5) The circuit device of claim 5, wherein the second sub-layer is adjacent to a second side of the second layer. ### Claim 7 (depends on 1) The circuit device of claim 1, wherein the first sub-layer spans at least 30% of the thickness of the second layer, the second sub-layer spans at least 30% of the thickness of the second layer, and the difference between the first average grain size and the second average grain size is at least 30% of the first average grain size. ### Claim 8 (depends on 1) The circuit device of claim 1, wherein the second layer forms a first hole structure which extends through the second layer, wherein a first width of the first hole structure at the first sub-layer is smaller than a second width of the first hole structure at the second sub-layer. ### Claim 9 (depends on 8) The circuit device of claim 8, wherein the second layer further forms a second hole structure which extends through the second layer, wherein a first portion of the first sub-layer and a second portion of the second sub-layer each extend both to the first hole structure and to the second hole structure, wherein the first portion comprises the first average grain size, and wherein the second portion comprises the second average grain size. ### Claim 10 A method comprising: forming on a first dielectric layer a first sub-layer of a second layer of a metal, wherein at least a portion of the first sub-layer is formed based on a first metallization condition; forming a second sub-layer of the second layer, wherein at least a portion of the second sub-layer is formed based on a second metallization condition; and performing an etch through the second sub-layer toward the first sub-layer; wherein: the first sub-layer spans at least 5% of a thickness of the second layer; the second sub-layer spans at least 5% of the thickness of the second layer; a first average grain size of the first sub-layer is larger than a second average grain size of the second sub-layer, the second average grain size smaller than the first average grain size; and a difference between the first average grain size and the second average grain size is at least 10% of the first average grain size. ### Claim 11 (depends on 10) The method of claim 10, wherein a package substrate comprises the second layer. ### Claim 12 (depends on 11) The method of claim 11, wherein a core of the package substrate comprises the second layer. ### Claim 13 (depends on 10) The method of claim 10, wherein the first sub-layer adjoins the second sub-layer. ### Claim 14 (depends on 10) The method of claim 10, further comprising: forming a third sub-layer of the second layer, wherein a difference between a third average grain size of the third sub-layer and the second average grain size is at least 10% of the third average grain size. ### Claim 15 (depends on 10) The method of claim 10, wherein the first sub-layer is adjacent to a first side of the second layer. ### Claim 16 (depends on 10) The method of claim 10, wherein the first sub-layer spans at least 30% of the thickness of the second layer, the second sub-layer spans at least 30% of the thickness of the second layer, and the difference between the first average grain size and the second average grain size is at least 30% of the first average grain size. ### Claim 17 (depends on 10) The method of claim 10, wherein the first metallization condition comprises a first level of an electroplating current wherein the second metallization condition comprises a second level of the electroplating current. ### Claim 18 (depends on 10) The method of claim 10, wherein the first metallization condition comprises a first chemical composition of an electroless plating solution, and wherein the second metallization condition comprises a second chemical composition of the electroless plating solution. ### Claim 19 (depends on 10) The method of claim 10, wherein the first metallization condition comprises an electroplating process, and wherein the second metallization condition comprises an electroless deposition process. ### Claim 20 A system comprising: a circuit device comprising: a first layer comprising a dielectric; and a second layer of a metal on the first layer, the second layer comprising: a first sub-layer of the metal, the first sub-layer comprising a first average grain size, wherein the first sub-layer spans at least 5% of a thickness of the second layer; a second sub-layer of the metal, the second sub-layer comprising a second average grain size, wherein the second sub-layer spans at least 5% of the thickness of the second layer, the second average grain size smaller than the first average grain size; and a third sub-layer of the metal, the third sub-layer comprising a third average grain size, wherein the third sub-layer spans at least 5% of the thickness of the second layer; wherein: a first difference between the first average grain size and the second average grain size is at least 10% of the first average grain size; and a second difference between the third average grain size and the second average grain size is at least 10% of the third average grain size; and a circuit board coupled to the circuit device, the circuit board to communicate a signal a metallization structure of the second layer.