# US 11,116,072 B2 · Discrete circuit having cross-talk noise cancellation circuitry and method thereof

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- Number: US 11,116,072 B2
- Document ID: US11116072B2
- Status: Granted
- Kind: B2
- Application number: 15/817,098
- Filed: 2017-11-17
- Published: 2019-02-07
- Granted: 2021-09-07
- Earliest claimed: 2017-07-05
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Jun Liao; Zhen Zhou; James A. McCall; Jong-Ru Guo; Xiang Li; Yunhui Chu; Zuoguo Wu
- Web page: https://patentgrep.com/patent/US11116072B2

## CPC

- H05K 1/0228: {Compensation of cross-talk by a mutually correlated lay-out of printed circuit traces, e.g. for compensation of cross-talk in mounted connectors (balanced signal pairs H05K1/0245)}
- H04B 3/32: Reducing cross-talk, e.g. by compensating
- H05K 1/145: {Arrangements wherein electric components are disposed between and simultaneously connected to two planar printed circuit boards, e.g. Cordwood modules}
- H05K 2201/09227: Layout details of a plurality of traces, e.g. escape layout for Ball Grid Array [BGA] mounting
- H10W 44/20: at high-frequency [HF] or radio frequency [RF]
- H10W 70/682: {comprising holes having chips therein}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H04B: TRANSMISSION
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

An apparatus is described. The apparatus includes a semiconductor chip having cross-talk noise cancellation circuitry disposed between a disturber trace and a trace to be protected from cross-talk noise emanating from the disturber trace. The trace is to be coupled to a receiver disposed on a different semiconductor chip.

## Claims

### Claim 1

An apparatus, comprising:
a semiconductor chip to be disposed between a transmitting semiconductor chip and a receiving semiconductor chip, the semiconductor chip comprising cross-talk noise cancellation circuitry disposed between a disturber trace and a trace to be protected from cross-talk noise emanating from said disturber trace, said trace to be protected from cross-talk noise emanating from said disturber trace to be coupled to a receiver disposed on the receiving semiconductor chip, wherein, a first signal that is to propagate on said disturber trace is to be received by said semiconductor chip at a first input of said semiconductor chip, and wherein, a second signal that is to propagate on said trace to be protected from cross-talk noise emanating from said disturber trace is to be received by said semiconductor chip at a second input of said semiconductor chip, wherein, at least one of said first and second signals are driven by said transmitting semiconductor chip, wherein said disturber trace and said trace to be protected from cross-talk noise emanating from said disturber trace are components of a memory channel.

### Claim 2 (depends on 1)

The apparatus of claim 1 wherein said semiconductor chip is disposed on a DIMM card and said receiving semiconductor chip is a memory semiconductor chip.

### Claim 3 (depends on 1)

The apparatus of claim 1 wherein said semiconductor chip is a re-driver semiconductor chip.

### Claim 4 (depends on 1)

The apparatus of claim 1 wherein said semiconductor chip is a re-timer semiconductor chip.

### Claim 5 (depends on 1)

The apparatus of claim 1 wherein said semiconductor chip is an interposer that is to be located between a substrate and said receiving semiconductor chip in a stacked chip arrangement.

### Claim 6 (depends on 1)

The apparatus of claim 1 wherein said disturber trace and said trace to be protected from cross-talk noise emanating from said disturber trace are to be coupled to wires in a cable.

### Claim 7 (depends on 1)

The apparatus of claim 1 wherein said receiving semiconductor chip is a multi-core processor semiconductor chip.

### Claim 8 (depends on 2)

The apparatus of claim 2 wherein said semiconductor chip comprises a buffer circuit.

### Claim 9 (depends on 5)

The apparatus of claim 5 wherein said semiconductor chip is part of a test apparatus comprising I/O pins.

### Claim 10 (depends on 8)

The apparatus of claim 8 wherein said buffer circuit is to buffer DQ and/or DQS signals.

### Claim 11

A computing system, comprising:
a plurality of processing cores;
a system memory;
a memory controller coupled between said plurality of processing cores and said system memory;
a trace;
a disturber trace;
a semiconductor chip disposed between a transmitting semiconductor chip and a receiving semiconductor chip, the semiconductor chip comprising cross-talk noise cancellation circuitry disposed between said disturber trace and said trace, said trace to be protected from cross-talk noise emanating from said disturber trace by said cross-talk noise cancellation circuitry, said trace to be protected from cross-talk noise emanating from said disturber trace to be coupled to a receiver disposed on said receiving semiconductor chip, wherein, a first signal that is to propagate on said disturber trace is to be received by said semiconductor chip at a first input of said semiconductor chip, and wherein, a second signal that is to propagate on said trace to be protected from cross-talk noise emanating from said disturber trace is to be received by said semiconductor chip at a second input of said semiconductor chip, wherein, at least one of said first and second signals are driven by said transmitting semiconductor chip.

### Claim 12 (depends on 11)

The computing system of claim 11 wherein said semiconductor chip is disposed on a DIMM card and said receiving semiconductor chip is a memory semiconductor chip.

### Claim 13 (depends on 11)

The computing system of claim 11 wherein said disturber trace and said trace to be protected from cross-talk noise emanating from said disturber trace are components of a memory channel.

### Claim 14 (depends on 11)

The computing system of claim 11 wherein said plurality of processing cores and said memory controller are disposed on a multi-core processor semiconductor chip.

### Claim 15 (depends on 12)

The computing system of claim 12 wherein said semiconductor chip comprises a buffer circuit.

### Claim 16 (depends on 13)

The computing system of claim 13 wherein said semiconductor chip is a re-driver semiconductor chip.

### Claim 17 (depends on 13)

The computing system of claim 13 wherein said semiconductor chip is a re-timer semiconductor chip.

### Claim 18 (depends on 15)

The computing system of claim 15 wherein said buffer circuit is to buffer DQ and/or DQS signals.

### Claim 19

A method for transmitting and receiving memory signals, comprising:
transmitting a first signal and a second signal from a transmitting semiconductor chip;
receiving the first signal at another semiconductor chip;
receiving the second signal at the another semiconductor chip;
propagating the first signal on a first trace on the another semiconductor chip;
propagating the second signal on a second trace on the another semiconductor chip, wherein said first trace and said second trace are components of a memory channel;
cancelling out from the second signal, on the another semiconductor chip, cross-talk noise emanating from the first signal; and,
sending the second signal after the cancelling out from the another semiconductor chip to a receiver on a receiving semiconductor chip.