# US 11,116,070 B2 · Interconnect circuit methods and devices > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,116,070 B2 - Document ID: US11116070B2 - Status: Granted - Kind: B2 - Application number: 16/034,899 - Filed: 2018-07-13 - Published: 2019-01-17 - Granted: 2021-09-07 - Earliest claimed: 2017-07-13 - Assignees: CelLink Corporation - Applicants: CelLink Corporation - Inventors: Kevin Michael Coakley; Malcolm Parker Brown; Dongao Yang; Michael Lawrence Miller; Paul Henry Lego - Web page: https://patentgrep.com/patent/US11116070B2 ## CPC - H05K 3/4623: {the circuit boards having internal via connections between two or more circuit layers before lamination, e.g. double-sided circuit boards (H05K3/462 takes precedence)} - H05K 3/007: {Manufacture or processing of a substrate for a printed circuit board supported by a temporary or sacrificial carrier (H05K1/187, H05K3/20 and H05K3/4682 take precedence)} - H05K 3/0073: {Masks not provided for in groups H05K3/02 - H05K3/46, e.g. for photomechanical production of patterned surfaces} - H05K 3/06: the conductive material being removed chemically or electrolytically, e.g. by photo-etch process {(semi-additive methods H05K3/108)} - H05K 3/20: by affixing prefabricated conductor pattern {(H05K1/187, H05K3/046, H05K3/4658, H05K3/4682 takes precedence)} - H05K 3/281: {by means of a preformed insulating foil (H05K3/284 takes precedence)} - H01M 50/519: comprising printed circuit boards [PCB] - H05K 1/0201: {Thermal arrangements, e.g. for cooling, heating or preventing overheating} - H05K 1/118: {specially for flexible printed circuits, e.g. using folded portions} - H05K 3/046: {by selective transfer or selective detachment of a conductive layer} - H05K 3/064: {Photoresists} - H05K 3/44: Manufacturing insulated metal core circuits {or other insulated electrically conductive core circuits (H05K3/0058, H05K3/4608, and H05K3/4641 take precedence)} - H05K 3/445: {having insulated holes or insulated via connections through the metal core} - H05K 2201/0145: Polyester, e.g. polyethylene terephthalate [PET], polyethylene naphthalate [PEN] - H05K 2201/015: Fluoropolymer, e.g. polytetrafluoroethylene [PTFE] - H05K 2201/0154: Polyimide - H05K 2201/10037: Printed or non-printed battery - H05K 2203/0264: Peeling insulating layer, e.g. foil, or separating mask - H05K 2203/066: Transfer laminating of insulating material, e.g. resist as a whole layer, not as a pattern - Y02E 60/10: Energy storage using batteries - Y10T 29/49156: with selective destruction of conductive paths - H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS - H01M: PROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY - Y02E: REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION - Y10T: TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION ## Abstract Provided are interconnect circuits and methods of forming thereof. A method may involve laminating a substrate to a conductive layer followed by patterning the conductive layer. This patterning operation forms individual conductive portions, which may be also referred to as traces or conductive islands. The substrate supports these portions relative to each other during and after patterning. After patterning, an insulator may be laminated to the exposed surface of the patterned conductive layer. At this point, the conductive layer portions are also supported by the insulator, and the substrate may optionally be removed, e.g., together with undesirable portions of the conductive layer. Alternatively, the substrate may be retained as a component of the circuit and the undesirable portions of the patterned conductive layer may be removed separately. These approaches allow using new patterning techniques as well as new materials for substrates and/or insulators. ## Claims ### Claim 1 A method of forming an interconnect circuit, the method comprising: laminating a substrate to a conductive layer, wherein the conductive layer is a metal foil, comprising a first side and a second side, opposite of the first side, and having a constant thickness, and wherein the substrate comprises an adhesive layer, laminated to the second side of the conductive layer; patterning the conductive layer, while the conductive layer remains laminated to the substrate, wherein patterning the conductive layer forms a first conductive portion and a second conductive portion of the conductive layer, at least partially separated from the first conductive portion, wherein the substrate maintains orientation of the first conductive portion relative to the second conductive portion after patterning the conductive layer; after patterning the conductive layer, laminating a first insulator to the first side of the conductive layer; and after laminating the first insulator to the first side of the conductive layer, removing the substrate from the conductive layer, wherein the first insulator maintains the orientation of the first conductive portion relative to the second conductive portion after the substrate is removed. ### Claim 2 (depends on 1) The method of claim 1, wherein the first insulator comprises an opening prior to laminating the first insulator to the conductive layer. ### Claim 3 (depends on 2) The method of claim 2, wherein the opening at least partially overlaps with the first conductive portion of the conductive layer such that the first side of the first conductive portion remains at least partially exposed after laminating to the first insulator. ### Claim 4 (depends on 3) The method of claim 3, wherein a portion of the first insulator forming the opening is laminated to the first side of the first conductive portion. ### Claim 5 (depends on 1) The method of claim 1, wherein patterning the conductive layer further forms a third portion of the conductive layer positioned between the first conductive portion and the second conductive portion of the conductive layer, and wherein the method further comprises removing the third portion of the conductive layer from the substrate prior to laminating the first insulator to the first side of the conductive layer. ### Claim 6 (depends on 1) The method of claim 1, wherein patterning the conductive layer further forms a third portion of the conductive layer positioned between the first conductive portion and the second conductive portion of the conductive layer, and wherein the method further comprises removing the third portion of the conductive layer after laminating the first insulator to the first side of the conductive layer. ### Claim 7 (depends on 6) The method of claim 6, wherein the third portion of the conductive layer is removed while removing the substrate from the conductive layer. ### Claim 8 (depends on 6) The method of claim 6, wherein the third portion of the conductive layer is removed after removing the substrate from the conductive layer. ### Claim 9 (depends on 6) The method of claim 6, wherein the third portion is connected to each of the first conductive portion and the second conductive portion and operable to support the first conductive portion and the second conductive portion. ### Claim 10 (depends on 1) The method of claim 1, wherein patterning the conductive layer completely removes a portion of the conductive layer positioned between the first conductive portion and the second conductive portion. ### Claim 11 (depends on 1) The method of claim 1, wherein patterning the conductive layer forms one or more pattern openings in the conductive layer, wherein the one or more pattern openings are disposed between the between the first conductive portion and the second conductive portion of the conductive layer. ### Claim 12 (depends on 11) The method of claim 11, wherein each of the one or more pattern openings comprises tapered side walls. ### Claim 13 (depends on 11) The method of claim 11, wherein each of the one or more pattern openings comprises substantially parallel side walls. ### Claim 14 (depends on 13) The method of claim 13, wherein the substantially parallel side walls protrude above a portion of the first side of the conductive layer positioned away from the one or more pattern openings. ### Claim 15 (depends on 11) The method of claim 11, wherein at least one of the one or more pattern openings have a variable width. ### Claim 16 (depends on 1) The method of claim 1, wherein patterning the conductive layer comprises a process selected from the group consisting of chemical etching, electrochemical etching, mechanical cutting, laser cutting, and laser ablation. ### Claim 17 (depends on 1) The method of claim 1, wherein removing the substrate further comprises deactivating at least a portion of the adhesive layer. ### Claim 18 (depends on 17) The method of claim 17, wherein at least the portion of the adhesive layer, deactivated while removing the substrate, overlaps with the first conductive portion and the second conductive portion of the conductive layer. ### Claim 19 (depends on 18) The method of claim 18, wherein a remaining portion of the adhesive layer, different from at least the portion of the adhesive layer deactivated while removing the substrate, remains activated. ### Claim 20 (depends on 19) The method of claim 19, wherein patterning the conductive layer further forms a third portion of the conductive layer positioned between the first conductive portion and the second conductive portion of the conductive layer, wherein the remaining portion of the adhesive layer overlaps with the third portion of the conductive layer, and wherein the method further comprises removing the third portion of the conductive layer while removing the substrate.