# US 11,115,693 B2 · Source clock recovery in wireless video systems

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- Number: US 11,115,693 B2
- Document ID: US11115693B2
- Status: Granted
- Kind: B2
- Application number: 16/367,090
- Filed: 2019-03-27
- Published: 2020-10-01
- Granted: 2021-09-07
- Earliest claimed: 2019-03-27
- Assignees: Advanced Micro Devices, Inc.
- Applicants: Advanced Micro Devices, Inc.
- Inventors: Stephen Mark Ryan; Carson Ryley Reece Green
- Web page: https://patentgrep.com/patent/US11115693B2

## CPC

- H04N 21/242: Synchronisation processes, e.g. processing of PCR [Programme Clock References] {(arrangements for synchronising broadcast or distribution via plural systems in broadcast distribution systems H04H20/18)}
- H04N 21/23805: {Controlling the feeding rate to the network, e.g. by controlling the video pump}
- H04N 21/2402: {Monitoring of the downstream path of the transmission network, e.g. bandwidth available (traffic monitoring in data switching networks H04L43/00; monitoring data switching networks utilization H04L43/0876)}
- H04N 21/4305: {Synchronising client clock from received content stream, e.g. locking decoder clock with encoder clock, extraction of the PCR packets (arrangements for synchronising receiver with transmitter by comparing receiver clock with transmitter clock H04L7/0012; arrangements for synchronising receiver with transmitter wherein the receiver takes measures against momentary loss of synchronisation H04L7/0083)}
- H04H 20/18: Arrangements for synchronising broadcast or distribution via plural systems
- H04N 21/43637: {involving a wireless protocol, e.g. Bluetooth®, RF or wireless LAN [IEEE 802.11] (arrangements for wireless networking or broadcasting of information in indoor or near-field type systems H04B10/114)}
- H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04H: BROADCAST COMMUNICATION (multiplex communication H04J; pictorial communication aspects of broadcast systems H04N)

## Abstract

Systems, apparatuses, and methods for performing efficient video transmission are disclosed. In a video processing system, a transmitter sends encoded pixel data to a receiver. The receiver stores the encoded pixel data in a buffer at an input data rate. A decoder of the receiver reads the pixel data from the buffer at an output data rate. Each of a transmitter and the receiver maintains a respective synchronization counter. When detecting a start of a frame, each of the transmitter and the receiver stores a respective frame start count as a copy of a current value of the respective synchronization counter. The transmitter sends its frame start count to the receiver. The receiver determines a difference between the respective frame start counts, and adjusts the decoding rate based on the difference.

## Claims

### Claim 1

A receiver comprising:
a transceiver configured to receive encoded pixels of frames; and
logic configured to:
detect a start of frame and a corresponding transmitter counter value in wirelessly received data, wherein the transmitter counter value corresponds to a time at which an encoder of the transmitter detected the start of frame;
capture a receiver counter value responsive to a decoder of the receiver detecting the start of frame;
compare the transmitter counter value to the receiver counter value; and
adjust a pixel decoding rate of a decoder in the receiver based on a difference between the transmitter counter value and the receiver counter value.

### Claim 2 (depends on 1)

The receiver as recited in claim 1, wherein
the transmitter counter value is a copy of a value of a timing synchronization function (TSF) counter in the transmitter; and
the receiver counter value is a copy of a value of a TSF counter in the receiver.

### Claim 3 (depends on 2)

The receiver as recited in claim 2, wherein the copy of the value of the synchronization counter in the transmitter is a value of the TSF counter in the transmitter at a time of detecting a start of the frame in the transmitter.

### Claim 4 (depends on 3)

The receiver as recited in claim 3, wherein the logic is further configured to add an estimated propagation latency value to the transmitter counter value prior to determining said difference.

### Claim 5 (depends on 3)

The receiver as recited in claim 3, wherein in response to determining a decoder in the receiver is enabled, the logic is further configured to capture the receiver counter value by capturing a copy of the value of the synchronization counter in the receiver at a detected start of a frame in the receiver.

### Claim 6 (depends on 3)

The receiver as recited in claim 3, wherein in response to determining a decoder in the receiver is disabled, the logic is further configured to capture the receiver counter value by capturing a copy of the value of the synchronization counter in the receiver at a time of detecting the corresponding transmitter counter value in wirelessly received data.

### Claim 7 (depends on 6)

The receiver as recited in claim 6, wherein in further response to determining the decoder is disabled, the logic is further configured to enable the decoder after a delay based on a difference between the corresponding transmitter counter value and the captured receiver counter value.

### Claim 8 (depends on 1)

The receiver as recited in claim 1, wherein the receiver is configured to:
receive the wirelessly received data including the start of frame and corresponding transmitter counter value in a first type of frame; and
periodically receive a value of the transmitter counter in a second type of frame, different from the first type of frame, during a clock synchronization protocol.

### Claim 9 (depends on 1)

The receiver as recited in claim 1, wherein to adjust the pixel decoding data rate, the logic is further configured to:
reduce the pixel decoding data rate, in response to determining the transmitter counter value is greater than the receiver counter value; and
increase the pixel decoding data rate, in response to determining the transmitter counter value is less than the receiver counter value.

### Claim 10

A method, comprising:
receiving, by a transceiver of a receiver, encoded pixels of frames from a transmitter;
detecting, by logic of the receiver, a start of frame and a corresponding transmitter counter value in wirelessly received data, wherein the transmitter counter value corresponds to a time at which an encoder of the transmitter detected the start of frame;
capturing, by the logic, a receiver counter value responsive to a decoder of the receiver detecting the start of frame;
comparing, by the logic, the transmitter counter value to the receiver counter value; and
adjusting, by the logic, a pixel decoding rate of a decoder in the receiver based on a difference between the transmitter counter value and the receiver counter value.

### Claim 11 (depends on 10)

The method as recited in claim 10, wherein
the transmitter counter value is a copy of a value of a timing synchronization function (TSF) counter in the transmitter; and
the receiver counter value is a copy of a value of a TSF counter in the receiver.

### Claim 12 (depends on 11)

The method as recited in claim 11, wherein the copy of the value of the TSF counter in the transmitter is a value of the TSF counter in the transmitter at a time of detecting a start of the frame in the transmitter.

### Claim 13 (depends on 12)

The method as recited in claim 12, further comprising adding an estimated propagation latency value to the transmitter counter value prior to determining said difference.

### Claim 14 (depends on 10)

The method as recited in claim 10, wherein to adjust the pixel decoding data rate, the method further comprises:
reducing the pixel decoding data rate, in response to determining the transmitter counter value is greater than the receiver counter value; and
increasing the pixel decoding data rate, in response to determining the transmitter counter value is less than the receiver counter value.

### Claim 15 (depends on 10)

The method as recited in claim 10, further comprising:
receiving the wirelessly received data including the start of frame and corresponding transmitter counter value in a first type of frame; and
periodically receiving a value of the transmitter counter in a second type of frame, different from the first type of frame, during a clock synchronization protocol.

### Claim 16

A system comprising:
a transmitter configured to:
encode pixels of frames; and
transmit the encoded pixels of frames; and
a receiver configured to:
receive wireless data including the encoded pixels of frames from the transmitter;
detect a start of frame and a corresponding transmitter counter value in the received wireless data, wherein the transmitter counter value corresponds to a time at which an encoder of the transmitter detected the start of frame;
capture a receiver counter value responsive to a decoder of the receiver detecting the start of frame;
compare the transmitter counter value to the receiver counter value; and
adjust a pixel decoding rate of a decoder in the receiver based on a difference between the transmitter counter value and the receiver counter value.

### Claim 17 (depends on 16)

The system as recited in claim 16, wherein
the transmitter counter value is a copy of a value of a timing synchronization function (TSF) counter in the transmitter; and
the receiver counter value is a copy of a value of a TSF counter in the receiver.

### Claim 18 (depends on 17)

The system as recited in claim 17, wherein the copy of the value of the TSF counter in the transmitter is a value of the TSF counter in the transmitter at a time of detecting a start of the frame in the transmitter.

### Claim 19 (depends on 18)

The system as recited in claim 18, wherein the receiver is further configured to add an estimated propagation latency value to the transmitter counter value prior to determining said difference.

### Claim 20 (depends on 16)

The system as recited in claim 16, wherein the receiver is further configured to:
receive the wirelessly received data including the start of frame and corresponding transmitter counter value in a first type of frame; and
periodically receive a value of the transmitter counter in a second type of frame, different from the first type of frame, during a clock synchronization protocol.