# US 11,115,614 B2 · Image sensor with A/D conversion circuit having reduced DNL deterioration

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 11,115,614 B2
- Document ID: US11115614B2
- Status: Granted
- Kind: B2
- Application number: 16/668,803
- Filed: 2019-10-30
- Published: 2020-06-18
- Granted: 2021-09-07
- Earliest claimed: 2018-12-13
- Assignees: Renesas Electronics Corporation
- Applicants: Renesas Electronics Corporation
- Inventors: Yoichi Iizuka; Fukashi Morishita
- Web page: https://patentgrep.com/patent/US11115614B2

## CPC

- H03M 1/34: Analogue value compared with reference values (H03M1/48 takes precedence)
- H03K 23/542: {with crossed-couplings, i.e. Johnson counters}
- H03M 1/123: {Simultaneous, i.e. using one converter per channel but with common control or reference circuits for multiple converters}
- H03M 1/145: {the steps being performed sequentially in series-connected stages (H03M1/141, H03M1/143, H03M1/16 take precedence)}
- H03M 1/56: Input signal compared with linear ramp
- H04N 25/60: Noise processing, e.g. detecting, correcting, reducing or removing noise
- H04N 25/78: Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION

## Abstract

The present invention provides a semiconductor device having an integration type A/D converter capable of speeding up. The semiconductor device includes a Johnson counter 18 for transmitting a lower bit counter signal JC<3:0>, a lower bit latch circuit 11 for outputting a lower bit latch result signal by a lower bit counter signal JC<3:0> and a lower bit latch signal 14, a determination circuit 12 for outputting an upper bit latch signal 15 by a lower bit latch signal 14, a binary gray converter circuit 20 for transmitting an upper bit counter signal GR<n:3>, and an upper bit latch circuit 13 for outputting an upper bit latch result signal by an upper bit counter signal GR<n:3> and an upper bit latch signal 15.

## Claims

### Claim 1

A semiconductor device comprising:
a lower counter circuit configured to output a lower bit counter signal;
an input signal determination circuit configured to compare a reference voltage with an input signal and output a lower bit latch signal;
a lower bit latch circuit configured to receive the lower bit counter signal and the lower bit latch signal to output a lower bit latch result signal;
a lower bit determination circuit configured to receive the lower bit counter signal and the lower bit latch signal to output an upper bit latch signal;
an upper counter circuit configured to output an upper bit counter signal; and
an upper bit latch circuit configured to receive the upper bit counter signal and the upper bit latch signal to output an upper bit latch result signal;
wherein each of the lower bit counter signal and the upper bit counter signal includes a plurality of bit counter signals,
wherein the lower bit latch circuit latches the lower bit counter signal in response to the lower bit latch signal, and
wherein the lower bit determination circuit outputs the upper bit latch signal in a period excluding an indefinite period in which the upper bit counter signal becomes indefinite, based on the lower bit latch signal and a predetermined bit counter signal in the lower bit counter signal.

### Claim 2

A semiconductor device comprising:
a reference voltage generation circuit for generating a reference voltage linearly varying with passage of time;
a counter circuit for generating a lower bit counter signal and an upper bit counter signal each of which has a value varying with the passage of time and each of which includes a plurality of bit counter signals; and
an integration type A/D converter circuit including
a comparator circuit for comparing an input signal with the reference voltage and outputting a lower bit latch signal when the input signal and the reference voltage reach a predetermined relationship,
a lower bit latch circuit for latching the lower bit counter signal in response to the lower bit latch signal,
a determination circuit for outputting an upper bit latch signal in a period excluding an indefinite period in which the upper bit counter signal becomes indefinite based on the lower bit latch signal and a predetermined bit counter signal in the lower bit counter signal, and
an upper bit latch circuit for latching the upper bit counter signal in response to the upper bit latch signal, wherein the upper bit counter signal latched in the upper bit latch circuit and the lower bit counter signal latched in the lower bit latch circuit are outputted as a digital signal corresponding to the input signal.

### Claim 3 (depends on 2)

The semiconductor device as claimed in claim 2,
wherein the lower bit counter signal includes a bit counter signal representing a smallest variation of an analogue signal to be converted by the integration type A/D converter circuit.

### Claim 4 (depends on 3)

The semiconductor device as claimed in claim 3,
wherein the integration type A/D converter circuit includes a decoder circuit for decoding the upper bit counter signal latched in the upper bit latch circuit and the lower bit counter signal latched in the lower bit latch circuit as one digital signal.

### Claim 5 (depends on 4)

The semiconductor device as claimed in claim 4,
wherein the determination circuit is supplied with a plurality of bit counter signals in the lower bit counter signal as a predetermined bit counter signal.

### Claim 6 (depends on 4)

The semiconductor device as claimed in claim 4,
wherein the counter circuit includes:
a lower bit counter circuit outputting the lower bit counter signal; and
an upper bit counter circuit outputting the upper bit counter signal based on a bit counter signal outputted from the lower bit counter circuit.

### Claim 7 (depends on 6)

A semiconductor device as claimed in claim 6,
wherein the lower bit counter circuit comprises a Johnson counter for outputting a plurality of signals having phases different from each other as the lower bit counter signal, and
the upper bit counter circuit includes a counter circuit for counting a predetermined signal among a plurality of signals outputted from the Johnson counter and outputting a gray-coded signal as the upper bit counter signal.

### Claim 8 (depends on 2)

The semiconductor device as claimed in claim 2,
wherein the counter circuit includes:
a lower bit counter circuit for outputting the lower bit counter signal;
an upper bit counter circuit for outputting the upper bit counter signal based on the lower bit counter signal outputted from the lower bit counter circuit; and
a phase divider circuit for dividing a phase between the bit counter signals outputted from the lower bit counter circuit and outputting a divided bit counter signal representing a smallest variation of an analogue signal to be converted in the integration type A/D converter circuit, and
wherein the lower bit latch circuit latches the lower bit counter signal and the divided bit counter signal in response to the lower bit latch signal.

### Claim 9

A system comprising:
a plurality of photosensitive elements arranged in a matrix;
a pixel portion having a plurality of signal lines arranged along a column of photosensitive elements arranged in a matrix, and coupled with photosensitive elements arranged in each column;
a reference voltage generation circuit for generating a reference voltage linearly varying with passage of time;
a counter circuit for outputting an upper bit counter signal and a lower bit counter signal each including a plurality of bit counter signals;
a plurality of counter signal lines, arranged along row of the photosensitive elements arranged in the matrix, for transmitting the upper bit counter signals and the lower bit counter signals; and
column converter unit, arranged along each column direction, having a plurality of signal lines arranged in each column and a plurality of integration type A/D converters arranged in each column;
wherein each of the plurality of integration type A/D converters includes a comparator outputs a lower bit latch signal comparing an input signal supplied from a corresponding signal line with the reference voltage,
a lower bit latch circuit latches lower bit counter signal transmitted from a counter signal line in response to the lower bit latch signal,
a determination circuit outputs an upper bit latch signal in a period excluding an indefinite period in which an upper bit latch signal becomes indefinite based on the lower bit latch signal and a predetermined bit counter signal in the lower bit counter signal, and
an upper bit latch circuit latches an upper bit counter signal transmitted from a counter signal line in response to the upper bit latch signal.

### Claim 10 (depends on 9)

The system as claimed in claim 9,
wherein the counter circuit includes
a first counter circuit for outputting the lower bit counter signal,
a second counter circuit for generating the upper bit counter signal based on a bit counter signal outputted from the first counter circuit at a lower speed than the first counter circuit, and
wherein the system further comprises a decoder circuit for receiving the upper bit counter signal latched in the upper bit latch circuit and the lower bit counter signal latched in the lower bit latch circuit, and
wherein the decoder circuit outputs a digital signal corresponding to an input signal supplied from on photosensitive element through corresponding one signal line.

### Claim 11 (depends on 9)

The system as claimed in claim 9,
wherein the column conversion unit includes a phase division circuit arranged in a predetermined column, coupled to a counter signal line for transmitting the lower bit counter signal, for generating a divided bit counter signal dividing a phase difference between the lower bit counter signals, and
wherein the lower bit latch circuit latches the lower bit counter signal and the lower bit latch circuit latches the lower bit counter signal and the divided bit counter signal in response to the lower bit latch signal.