# US 11,115,611 B2 · Solid-state imaging device and imaging system

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- Number: US 11,115,611 B2
- Document ID: US11115611B2
- Status: Granted
- Kind: B2
- Application number: 15/930,152
- Filed: 2020-05-12
- Published: 2020-08-27
- Granted: 2021-09-07
- Earliest claimed: 2017-11-29
- Assignees: Nuvoton Technology Corporation Japan
- Applicants: Panasonic Semiconductor Solutions Co., Ltd.
- Inventors: Yosuke Higashi; Norihiko Sumitani
- Web page: https://patentgrep.com/patent/US11115611B2

## CPC

- H03M 1/145: {the steps being performed sequentially in series-connected stages (H03M1/141, H03M1/143, H03M1/16 take precedence)}
- H03M 1/56: Input signal compared with linear ramp
- H03M 1/64: with intermediate conversion to phase of sinusoidal {or similar periodical} signals
- H04N 25/78: Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
- H03M 1/123: {Simultaneous, i.e. using one converter per channel but with common control or reference circuits for multiple converters}
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)
- H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION

## Abstract

A solid-state imaging device includes a first converter which converts an analog signal representing a pixel value to an upper bit of a digital signal, and a second converter which converts the analog signal to a lower bit of the digital signal. The second converter includes a first latch circuit which latches, as phase information, a plurality of clock signals having different phases upon conversion to the upper bit in the first converter, a conversion circuit which generates the lower bit of the digital signal by converting the phase information to a binary value, and an adder, and a second latch circuit which latches an addition result of the adder. The adder adds the binary value converted by the conversion circuit and a value latched by the second latch circuit.

## Claims

### Claim 1

A solid-state imaging device, comprising:
a first converter which converts an analog signal representing a pixel value to an upper bit of a digital signal including the upper bit and a lower bit; and
a second converter which converts the analog signal to the lower bit of the digital signal,
wherein the second converter includes:
a first latch circuit which latches, as phase information, a plurality of clock signals upon conversion to the upper bit in the first converter, the plurality of clock signals having different phases;
a conversion circuit which generates the lower bit of the digital signal by converting the phase information to a binary value;
an adder; and
a second latch circuit which latches an addition result of the adder, and
the adder adds the binary value converted by the conversion circuit and a value latched by the second latch circuit.

### Claim 2 (depends on 1)

The solid-state imaging device according to claim 1,
wherein the first converter includes:
a comparison circuit which compares a level of an analog ramp signal to a level of the analog signal; and
a counter which generates the upper bit of the digital signal from the analog signal by counting time until the level of the analog ramp signal matches the level of the analog signal in a comparison result.

### Claim 3 (depends on 2)

The solid-state imaging device according to claim 2,
wherein the plurality of clock signals is m clock signals, where m is an integer of 2 or more, and
the first latch circuit latches m-bit phase information.

### Claim 4 (depends on 3)

The solid-state imaging device according to claim 3,
wherein the adder includes (m−1) full adders, and
the second latch circuit latches an (m−1)·bit addition result, which is the addition result of the adder.

### Claim 5 (depends on 3)

The solid-state imaging device according to claim 3,
wherein the conversion circuit converts the phase information having 2(m-1) different phases to an (m−1)·bit binary value.

### Claim 6 (depends on 2)

The solid-state imaging device according to claim 2,
wherein the counter generates the upper bit of the digital signal by counting time from start of change in the analog ramp signal to inversion of the comparison result signal using a reference clock signal among the plurality of clock signals.

### Claim 7 (depends on 2)

The solid-state imaging device according to claim 2, further comprising:
a signal selection circuit which switches a signal to be input to a clock inputter of the counter between a clock signal for a counter and a carry signal of an uppermost bit of the adder according to a control signal.

### Claim 8 (depends on 2)

The solid-state imaging device according to claim 2, further comprising:
a switch selector which converts the binary value from the conversion circuit to a complement of 2, and selectively outputs one of the complement of 2 and the binary value to the adder.

### Claim 9 (depends on 2)

The solid-state imaging device according to claim 2, further comprising:
a third latch circuit which latches a carry signal of an uppermost bit of the adder,
wherein using the comparison result signal as a clock signal for the third latch circuit, the third latch circuit latches the carry signal of the uppermost bit of the adder when the comparison result signal is inverted.

### Claim 10 (depends on 2)

The solid-state imaging device according to claim 2,
wherein the counter counts in any of an up-count mode and a down-count mode according to a control signal.

### Claim 11 (depends on 1)

An imaging system, comprising:
the solid-state imaging device according to claim 1; and
an image signal processor which performs image processing on an output signal of the solid-state imaging device.