# US 11,115,181 B2 · Memory device, host device, and memory system

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- Number: US 11,115,181 B2
- Document ID: US11115181B2
- Status: Granted
- Kind: B2
- Application number: 16/799,836
- Filed: 2020-02-25
- Published: 2020-06-18
- Granted: 2021-09-07
- Earliest claimed: 2015-07-22
- Assignees: MegaChips Corporation
- Applicants: MegaChips Corporation
- Inventors: Takahiko Sugahara; Hiromu Yutani
- Web page: https://patentgrep.com/patent/US11115181B2

## CPC

- H04L 9/003: {for power analysis, e.g. differential power analysis [DPA] or simple power analysis [SPA]}
- G06F 21/606: {by securing the transmission between two devices or processes}
- G06F 21/79: in semiconductor storage media, e.g. directly-addressable memories
- G06F 21/85: interconnection devices, e.g. bus-connected or in-line devices
- G09C 1/00: Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system (cryptographic typewriters G09C3/00)
- H04L 9/0656: {Pseudorandom key sequence combined element-for-element with data sequence, e.g. one-time-pad [OTP] or Vernam's cipher}
- G06F 2221/2123: Dummy operation
- H04L 2209/08: Randomization, e.g. dummy operations or using noise
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G09C: CIPHERING OR DECIPHERING APPARATUS FOR CRYPTOGRAPHIC OR OTHER PURPOSES INVOLVING THE NEED FOR SECRECY

## Abstract

A control circuit causes a first cryptographic module to perform a dummy operation in a command processing period and a data processing period in which a second cryptographic module performs a normal operation while the first cryptographic module does not perform a normal operation.

## Claims

### Claim 1

A memory device configured to be connected to a host device, comprising:
a first cryptographic module including circuitry and a second cryptographic module including circuitry, the first and second cryptographic modules each configured to perform a normal operation to encrypt and decrypt data to be transmitted and received between the host device and the memory device,
a third cryptographic module including circuitry and configured to perform a dummy operation based on dummy key information, and
a control circuit configured to control an operation of the third cryptographic module, the control circuit being configured to cause the third cryptographic module to perform a dummy operation in a period in which one of the first cryptographic module and the second cryptographic module performs a normal operation, wherein
the first cryptographic module includes a first temporary data generation circuit configured to generate temporary data based on input data,
the second cryptographic module includes a first encryption circuit configured to perform encryption based on the temporary data generated by the first temporary data generation circuit,
the third cryptographic module includes a second temporary data generation circuit configured to generate temporary data based on dummy input data and a second encryption circuit configured to perform encryption based on the temporary data generated by the second temporary data generation circuit, and
the control circuit is configured to cause the second encryption circuit to perform a dummy operation in a period in which only the first temporary data generation circuit of the first temporary data generation circuit and the first encryption circuit performs a normal operation, while causing the second temporary data generation circuit to perform a dummy operation in a period in Which only the first encryption circuit of the first temporary data generation circuit and the first encryption circuit performs a normal operation.

### Claim 2 (depends on 1)

The memory device according to claim 1, wherein
the control circuit is further configured to cause the first cryptographic module to perform a dummy operation in a period in which the second cryptographic module performs a normal operation while the first cryptographic module does not perform a normal operation.

### Claim 3 (depends on 2)

The memory device according to claim 2, wherein
the control circuit is further configured to cause the third cryptographic module to perform a dummy operation in a period in which both of the first cryptographic module and the second cryptographic module perform a normal operation concurrently.

### Claim 4 (depends on 1)

The memory device according to claim 1, wherein
the dummy input data has a fixed value.

### Claim 5 (depends on 1)

The memory device according to claim 1, wherein
the dummy input data has a variable value.

### Claim 6 (depends on 1)

The memory device according to claim 1, wherein
the input data is key information.

### Claim 7 (depends on 1)

The memory device according to claim 1, further comprising:
an unauthorized access detection circuit configured to detect an unauthorized access from the host device, wherein the control circuit is configured to cause the third cryptographic module to perform a dummy operation if the unauthorized access detection circuit detects the unauthorized access.

### Claim 8

A host device configured to accept a memory device, comprising:
a first cryptographic module including circuitry and a second cryptographic module including circuitry, the first and second cryptographic modules each configured to perform a normal operation to encrypt and decrypt data to be transmitted and received between the host device and the memory device,
a third cryptographic module including circuitry and configured to perform a dummy operation based on dummy key information, and
a control circuit configured to control an operation of the third cryptographic module, the control circuit being configured to cause the third cryptographic module to perform a dummy operation in a period in which one of the first cryptographic module and the second cryptographic module performs a normal operation, wherein
the first cryptographic module includes a first temporary data generation circuit configured to generate temporary data based on input data,
the second cryptographic module includes a first encryption circuit configured to perform encryption based on the temporary data generated by the first temporary data generation circuit,
the third cryptographic module includes a second temporary data generation circuit configured to generate temporary data based on dummy input data and a second encryption circuit configured to perform encryption based on the temporary data generated by the second temporary data generation circuit, and
the control circuit is configured to cause the second encryption circuit to perform a dummy operation in a period in which only the first temporary data generation circuit of the first temporary data generation circuit and the first encryption circuit performs a normal operation, while causing the second temporary data generation circuit to perform a dummy operation in a period in which only the first encryption circuit of the first temporary data generation circuit and the first encryption circuit performs a normal operation.

### Claim 9 (depends on 8)

The host device according to claim 8, wherein
the control circuit is further configured to cause the first cryptographic module to perform a dummy operation in a period in which the second cryptographic module performs a normal operation while the first cryptographic module does not perform a normal operation.

### Claim 10 (depends on 9)

The host device according to claim 9, wherein
the control circuit is further configured to cause the third cryptographic module to perform a dummy operation in a period in which both of the first cryptographic module and the second cryptographic module perform a normal operation concurrently.

### Claim 11 (depends on 8)

The host device according to claim 8, wherein
the dummy input data has a fixed value.

### Claim 12 (depends on 8)

The host device according to claim 8, wherein
the dummy input data has a variable value.

### Claim 13 (depends on 8)

The host device according to claim 8, wherein
the input data is key information.

### Claim 14

A memory system comprising:
a host device and
a memory device configured to be connected to the host device,
wherein the host device includes
a first cryptographic module including circuitry and a second cryptographic module including circuitry, the first and second cryptographic modules each configured to perform a normal operation to encrypt and decrypt data to be transmitted and received between the host device and the memory device,
a third cryptographic module including circuitry and configured to perform a dummy operation based on dummy key information, and
a first control circuit configured to control an operation of the third cryptographic module, the first control circuit being configured to cause the third cryptographic module to perform a dummy operation in a period in which one of the first cryptographic module and the second cryptographic module performs a normal operation, and
wherein the memory device includes
a fourth cryptographic module including circuitry and a fifth cryptographic module including circuitry, the fourth and fifth cryptographic modules each configured to perform a normal operation to encrypt and decrypt data to be transmitted and received between the host device and the memory device,
a sixth cryptographic module including circuitry and configured to perform a dummy operation based on dummy key information, and
a second control circuit configured to control an operation of the sixth cryptographic module, the second control circuit being configured to cause the sixth cryptographic module to perform a dummy operation in a period in which one of the fourth cryptographic module and the fifth cryptographic module performs a normal operation.