Clock and data recovery device and clock and data recovery method

Abstract

A clock and data recovery device includes a phase detector circuitry, an analog modulation circuitry, a serial-to-parallel converter circuit, a digital modulation circuitry, and an oscillator circuit. The phase detector circuitry detects a data signal according to first and second clock signals to generate an up signal and a down signal. The analog modulation circuitry generates a first adjustment signal according to the up signal and the down signal. The serial-to-parallel converter circuit generates a first control signal according to the up signal, and to generate a second control signal according to the down signal. The digital modulation circuitry generates a digital code according to the first and the second control signals, and to generate a second adjustment signal according to the digital code. The oscillator circuit generates the first and the second clock signals according to the first adjustment signal and the second adjustment signal.

Dependencies are inferred from the claim text.