# US 11,115,151 B1 · Method and apparatus for fast retraining of ethernet transceivers based on trickling error

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- Number: US 11,115,151 B1
- Document ID: US11115151B1
- Status: Granted
- Kind: B1
- Application number: 16/362,500
- Filed: 2019-03-22
- Granted: 2021-09-07
- Earliest claimed: 2019-03-22
- Assignees: Marvell Asia Pte Ltd
- Applicants: Aquantia Corporation
- Inventors: Seid Alireza Razavi Majomard; Hossein Sedarat
- Web page: https://patentgrep.com/patent/US11115151B1

## CPC

- H04L 1/0041: {Arrangements at the transmitter end}
- H04L 1/203: {Details of error rate determination, e.g. BER, FER or WER}
- H04L 1/0003: {by switching between different modulation schemes}
- H04L 1/0046: {Code rate detection or code type detection (H04L1/0038 takes precedence; detection of the data rate H04L25/0262; for packet format H04L1/0091)}
- H04L 1/0057: {Block codes (H04L1/0061, H04L1/0064 take precedence)}
- H04L 25/023: {with extension to other symbols}
- H04L 1/0045: {Arrangements at the receiver end}
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)

## Abstract

A method of operation for an Ethernet transceiver is disclosed. The method includes operating the Ethernet transceiver in a data mode, and triggering a fast retrain sequence of steps based on trickling error information. The triggering includes detecting error information, averaging the detected error information over a time interval to generate the trickling error information, comparing the averaged detected error information to a selected threshold value, and initiating the fast retrain sequence of steps based on the comparing.

## Claims

### Claim 1

A method of operation for an Ethernet transceiver, the method comprising:
operating the Ethernet transceiver in a data mode;
selecting a time interval for monitoring error information; and
triggering a fast retrain sequence by
detecting error information during the time interval,
averaging at least two non-consecutive frame errors in the detected error information over the time interval to generate trickling error information,
comparing the trickling error information to a selected threshold value, and
performing the fast retrain sequence-based on the comparing.

### Claim 2 (depends on 1)

The method according to claim 1, wherein the error information comprises an error predictor.

### Claim 3 (depends on 1)

The method according to claim 1, wherein the error information comprises Low-Density Parity Check (LDPC) error code information.

### Claim 4 (depends on 1)

The method according to claim 1, wherein the error information comprises LDPC loop iteration information.

### Claim 5 (depends on 1)

The method according to claim 1, further comprising:
operating the Ethernet transceiver in accordance with an NBASE-T Ethernet protocol.

### Claim 6 (depends on 1)

The method according to claim 1, further comprising:
prior to operating the Ethernet transceiver in the data mode, performing a full training sequence.

### Claim 7

An integrated circuit (IC) Ethernet transceiver chip comprising:
training logic to trigger a fast retrain sequence during a data mode, the training logic including
error detection circuitry to detect error information,
circuitry to average at least two non-consecutive frame errors in the detected error information over a user-selected time interval to generate trickling error information,
comparison circuitry to compare the trickling error information to a selected threshold value, and
circuitry to perform the fast retrain sequence based on the comparing.

### Claim 8 (depends on 7)

The IC Ethernet transceiver chip according to claim 7, wherein the error information comprises an error predictor.

### Claim 9 (depends on 7)

The IC Ethernet transceiver chip according to claim 7, wherein:
the error detection circuitry comprises low density parity check (LDPC) decoding circuitry.

### Claim 10 (depends on 7)

The IC Ethernet transceiver chip according to claim 7, wherein the error information comprises Low-Density Parity Check (LDPC) error code information.

### Claim 11 (depends on 7)

The IC Ethernet transceiver chip according to claim 7, wherein the error information comprises LDPC loop iteration information.

### Claim 12 (depends on 7)

The IC Ethernet transceiver chip according to claim 7, realized as an NBASE-T IC Ethernet transceiver chip.

### Claim 13

A method of operation for an Ethernet transceiver, the method comprising:
operating the Ethernet transceiver in a data mode;
selecting a time interval for monitoring error information;
establishing a consecutive frame error threshold and a trickling error threshold;
detecting error information;
averaging at least two non-consecutive frame errors in the error information over the time interval to generate trickling error information, and
triggering a fast retrain sequence based on a comparison of the trickling error information during the time interval to the consecutive frame error threshold and the trickling error threshold.

### Claim 14 (depends on 13)

The method according to claim 13, wherein the detecting error information comprises:
detecting an error predictor.

### Claim 15 (depends on 14)

The method according to claim 14, wherein the error predictor is based on a detected signal-to-noise ratio (SNR) along a channel coupled to the Ethernet transceiver.