# US 11,115,059 B2 · Encoding circuit, decoding circuit, encoding method, decoding method, and transmitting device

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- Number: US 11,115,059 B2
- Document ID: US11115059B2
- Status: Granted
- Kind: B2
- Application number: 16/996,967
- Filed: 2020-08-19
- Published: 2021-03-11
- Granted: 2021-09-07
- Earliest claimed: 2019-09-10
- Assignees: Fujitsu Limited
- Applicants: Fujitsu Limited
- Inventors: Kazumasa Mikami; Junichi Sugiyama
- Web page: https://patentgrep.com/patent/US11115059B2

## CPC

- H03M 13/253: {with concatenated codes}
- H03M 13/1108: {Hard decision decoding, e.g. bit flipping, modified or weighted bit flipping}
- H03M 13/1111: {Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms}
- H03M 13/118: {Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure (H03M13/1165 takes precedence)}
- H03M 13/25: Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM] {(modulation codes H03M13/31)}
- H03M 13/2906: {using block codes (H03M13/2957 takes precedence)}
- H03M 13/31: combining coding for error detection or correction and efficient use of the spectrum (without error detection or correction H03M5/14 {, H03M5/145})
- H03M 13/333: {Synchronisation on a multi-bit block basis, e.g. frame synchronisation}
- H04B 10/616: {Details of the electronic signal processing in coherent optical receivers}
- H04L 1/0041: {Arrangements at the transmitter end}
- H04L 1/0042: {Encoding specially adapted to other signal generation operation, e.g. in order to reduce transmit distortions, jitter, or to improve signal shape (H04L1/0067 takes precedence)}
- H04L 1/0045: {Arrangements at the receiver end}
- H04L 1/0057: {Block codes (H04L1/0061, H04L1/0064 take precedence)}
- H03M 13/1102: {Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes}
- H03M 13/1515: {Reed-Solomon codes}
- H03M 13/152: {Bose-Chaudhuri-Hocquenghem [BCH] codes}
- H03M 13/2957: {Turbo codes and decoding}
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)
- H04B: TRANSMISSION
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)

## Abstract

An encoding circuit includes an allocator configured to allocate symbols among a plurality of symbols within a constellation of multilevel modulation and correspond to values of a plurality of bit strings, a converter configured to convert values of each of bit strings excluding a first bit string so that, as a region within the constellation is closer to the center of the constellation, the number of symbols allocated in the region is larger, a switch configured to switch between a first time period in which a first error correction code is inserted and a second time period in which the first error correction code is not inserted, and an insertor configured to generate the first error correction code from a second bit string in the second time period and inserts the first error correction code in two or more bit strings in the first time period according to the switching.

## Claims

### Claim 1

An encoding circuit comprising:
an allocator configured to allocate, to a plurality of bit strings, symbols that are among a plurality of symbols within a constellation of multilevel modulation and correspond to values of the plurality of bit strings within a frame;
a converter configured to convert values of each of bit strings among the plurality of bit strings excluding a first bit string so that, as a region within the constellation is closer to the center of the constellation, the number of symbols allocated in the region among the plurality of symbols is larger;
a switch configured to switch, in a cycle of the frame, between a first time period in which a first error correction code to correct an error of the plurality of bit strings is inserted in the plurality of bit strings and a second time period in which the first error correction code is not inserted in the plurality of bit strings; and
a first insertor configured to generate the first error correction code from a second bit string among the plurality of bit strings in the second time period and inserts the first error correction code in two or more bit strings including the first bit string in the first time period in accordance with the switching by the switch.

### Claim 2 (depends on 1)

The encoding circuit according to claim 1, wherein
the first insertor inserts the first error correction code in two or more bit strings that are among the plurality of bit strings excluding the second bit string in the first time period.

### Claim 3 (depends on 1)

The encoding circuit according to claim 1, wherein
the first insertor inserts the first error correction code in two or more bit strings that are among the plurality of bit strings excluding a third bit string of a higher level than a level of the second bit string in the first time period.

### Claim 4 (depends on 1)

The encoding circuit according to claim 1, wherein
the first insertor inserts the first error correction code in each of the plurality of bit strings in the first time period.

### Claim 5 (depends on 1)

The encoding circuit according to any of claim 1, further comprising:
a second insertor configured to generate, from each of the plurality of bit strings, a second error correction code to correct an error of the plurality of bit strings and inserts the second error correction code in two or more bit strings including the first bit string in the first time period in accordance with the switching by the switching section, wherein
the first error correction code is used to correct an error of results of executing soft decision on the plurality of bit strings, and
the second error correction code is used to correct an error of results of executing hard decision on the plurality of bit strings.

### Claim 6

An encoding method comprising:
allocating, to a plurality of bit strings, symbols that are among a plurality of symbols within a constellation of multilevel modulation and correspond to values of the plurality of bit strings within a frame;
converting values of each of bit strings that are among the plurality of bit strings and exclude a first bit string so that, as a region within the constellation is closer to the center of the constellation, the number of symbols allocated in the region among the plurality of symbols is larger;
switching, in a cycle of the frame, between a first time period in which a first error correction code to correct an error of the plurality of bit strings is inserted in the plurality of bit strings and a second time period in which the first error correction code is not inserted in the plurality of bit strings; and
generating the first error correction code from a second bit string among the plurality of bit strings in the second time period and inserting the first error correction code in two or more bit strings including the first bit string in the first time period in accordance with the switching.

### Claim 7

A transmitting device comprising:
a circuit configured to:
allocate, to a plurality of bit strings, symbols that are among a plurality of symbols within a constellation of multilevel modulation and correspond to values of the plurality of bit strings within a frame,
convert values of each of bit strings that are among the plurality of bit strings excluding a first bit string so that, as a region within the constellation is closer to the center of the constellation, the number of symbols allocated in the region among the plurality of symbols is larger,
switch, in a cycle of the frame, between a first time period in which a first error correction code to correct an error of the plurality of bit strings is inserted in the plurality of bit strings and a second time period in which the first error correction code is not inserted in the plurality of bit strings, and
form a frame to be transmitted by generating the first error correction code from a second bit string among the plurality of bit strings in the second time period and inserting the first error correction code in two or more bit strings including the first bit string in the first time period in accordance with the switching; and
a transmitter configured to transmit, to another device, the frame converted to an optical signal and to be transmitted.

### Claim 8 (depends on 7)

The transmitting device according to claim 7 wherein,
the circuit further configured to:
execute, based on one of a plurality of symbols, soft decision on each of values of a plurality of bit strings within a frame to which the one of the plurality of symbols within a constellation of the multilevel modulation is allocated,
correct an error of results of the soft decision based on a first error correction code inserted in two or more bit strings that are among the plurality of bit strings and include a first bit string,
execute, based on the one symbol, hard decision on values of each of bit strings that are among the plurality of bit strings and exclude a second bit string,
inversely convert values of each of bit strings that exclude the first bit string and have been converted so that, as a region within the constellation is closer to the center of the constellation, the number of symbols allocated in the region among the plurality of symbols is larger,
select a bit string to be input from a bit string that is among the plurality of bit strings and is not the second bit string and for which the error of the results of the soft decision has been corrected based on the first error correction code and a bit string that is among the plurality of bit strings and is not the second bit string and has been subjected to the hard decision by the second deciding section, and
form the frame to be received by selecting the bit string for which the error of the results of the soft decision has been corrected based on the first error correction code in a first time period and selecting the bit string subjected to the hard decision in a second time period according to the first time period in which the first error correction code is inserted in two or more bit strings including the first bit string and the second time period in which the first error correction code is not inserted in the two or more bit strings including the first bit string in a cycle of the frame.