# US 11,115,045 B2 · Adaptive analog-to-digital converter for pulsed signals based on multi-bit sigma-delta modulation > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,115,045 B2 - Document ID: US11115045B2 - Status: Granted - Kind: B2 - Application number: 16/759,531 - Filed: 2018-10-25 - Published: 2020-10-01 - Granted: 2021-09-07 - Earliest claimed: 2017-10-25 - Assignees: Arizona Board of Regents on Behalf of the University of Arizona - Applicants: Arizona Board of Regents On Behalf of the University of Arizona - Inventors: Lars R. Furenlid; Maria Ruiz-Gonzalez - Web page: https://patentgrep.com/patent/US11115045B2 ## CPC - H03M 3/424: {the quantiser being a multiple bit one} - H03M 3/464: {Details of the digital/analogue conversion in the feedback path} - H03M 3/496: {Details of sampling arrangements or methods} - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) ## Abstract A delta sigma modulator includes a summation circuit, at least one integrator, a multi-bit quantizer and a negative feedback circuit. The summation circuit is configured to produce a difference signal between an analog input signal and an analog feedback signal. The integrator is operatively coupled to the summation circuit to integrate the difference signal. The multi-bit quantizer is operatively coupled to the integrator to digitize the integrated signal to generate an N-bit digital output signal, N being an integer greater than 1. The negative feedback circuit operatively couples the multi-bit quantizer to the summation circuit. The negative feedback circuit includes a digital-to-analog converter arrangement for receiving the N-bit digital output signal and providing the analog feedback signal such that digital values of the N-bit digital output signal and values of the analog feedback encoded by the digital values have a non-linear relationship to one another. ## Claims ### Claim 1 A delta sigma modulator comprising: a summation circuit configured to produce a difference signal between an analog input signal and an analog feedback signal; at least one integrator operatively coupled to the summation circuit to integrate the difference signal; a multi-bit quantizer operatively coupled to the at least one integrator to digitize the integrated signal to generate an N-bit digital output signal, N being an integer greater than 1; and a negative feedback circuit operatively coupling the multi-bit quantizer to the summation circuit, the negative feedback circuit including a digital-to-analog converter arrangement for receiving the N-bit digital output signal and providing the analog feedback signal such that digital values of the N-bit digital output signal and values of the analog feedback encoded by the digital values have a non-linear relationship to one another. ### Claim 2 (depends on 1) The delta sigma modulator of claim 1, wherein the non-linear relationship between the digital values of the N-bit digital output signal and between the values of the analog feedback signal encoded by the digital values is adjustable. ### Claim 3 (depends on 1) The delta sigma modulator of claim 1, wherein the non-linear relationship between the digital values of the N-bit digital output signal and between the values of the analog feedback signal encoded by the digital values is programmable. ### Claim 4 (depends on 1) The delta sigma modulator of claim 1, wherein the non-linear relationship between the digital values of the N-bit digital output signal and between the values of the analog feedback signal encoded by the digital values is fixed. ### Claim 5 (depends on 1) The delta sigma modulator of claim 1, wherein the multi-bit quantizer includes a comparator arrangement configured to compare the integrated signal to at least three thresholds and generate an N-bit digital output signal that reflects which of the at least three thresholds were exceeded, a difference between at least two pairs of successive thresholds being unequal to one another. ### Claim 6 (depends on 1) The delta sigma modulator of claim 1, wherein the non-linear relationship between the digital values of the N-bit digital output signal and the values of the analog feedback signal encoded by the digital values is tailored to characteristics of the analog input signal to thereby produce an accurate representation of the analog input signal. ### Claim 7 (depends on 1) The delta sigma modulator of claim 1, wherein the non-linear relationship between the digital values of the N-bit digital output signal and the values of the analog feedback signal encoded by the digital values is tailored to characteristics of a detector that generates the analog input signal to thereby produce an accurate representation of the analog input signal. ### Claim 8 (depends on 1) The delta sigma modulator of claim 1, wherein the non-linear relationship between the digital values of the N-bit digital output signal and the values of the analog feedback signal encoded by the digital values is tailored based on application specific characteristics to thereby produce an accurate representation of the analog input signal. ### Claim 9 A method for digitizing an analog input signal, comprising: directing the analog input signal to an input of a multi-bit delta sigma modulator that generates an N-bit digital output signal, N being an integer greater than 1, wherein digital values of the N-bit digital output signal and values of the analog feedback encoded by the digital values have a non-linear relationship to one another; and adjusting the nonlinear relationship between the digital values of the N-bit digital output signal and the values of the analog feedback encoded by the digital values. ### Claim 10 (depends on 9) The method of claim 9, wherein the adjusting is performed based at least in part on characteristics of the analog input signal. ### Claim 11 (depends on 9) The method of claim 9, wherein the adjusting is performed based at least in part on characteristics of a detector that generates the analog input signal. ### Claim 12 (depends on 9) The method of claim 9, wherein the adjusting is performed based at least in part on application specific characteristics. ### Claim 13 (depends on 9) The method of claim 9 further comprising recovering the analog input signal from the N-bit digital output signal by applying a smoothing filter. ### Claim 14 (depends on 13) The method of claim 13 wherein applying a smoothing function includes applying a different smoothing filter to each modulation level. ### Claim 15 A delta sigma modulator comprising: a summation circuit configured to produce a difference signal between an analog input signal and an analog feedback signal; at least one integrator operatively coupled to the summation circuit to integrate the difference signal; a multi-bit quantizer operatively coupled to the at least one integrator to digitize the integrated signal to generate an N-bit digital output signal, N being an integer greater than 1; and a negative feedback circuit operatively coupling the multi-bit quantizer to the summation circuit, the negative feedback circuit including at least 2(N-1) digital-to-analog converters that are separately addressable by the N-bit digital output signal received from the multi-bit quantizer, wherein each DAC has a different scaling factor between a received value of the N-bit digital output signal and a corresponding output signal. ### Claim 16 (depends on 15) The delta sigma modulator of claim 15, wherein the negative feedback circuit includes 2N−1 digital-to-analog converters.