Back to results
US 11,115,042 B1Granted
Low pass filter embedded digital-to-analog converter
AssigneeBeken Corporation
InventorsDesheng Hu, Jiazhou Liu, Dawei Guo
Life of this patent
Estimating the term…
Abstract
A low pass filter embedded digital-to-analog converter including a first switch coupled to a first node that is coupled to a fourth switch and a first capacitor, a second switch coupled to a second node that is coupled to the first capacitor and a third switch, a negative input of a first operational amplifier coupled to a third node that is coupled to the third switch and a second capacitor, and an output port of the first operational amplifier coupled to a fourth node that is coupled to the second capacitor and the fourth switch.
Claims9
A circuit, comprising:
- a first switch coupled to a first node that is coupled to a fourth switch and a first parallel array of binary-weighted linear capacitors;
- a second switch coupled to a first voltage of common mode and a second node that is coupled to the first parallel array and a third switch;
- a positive input port of a second operational amplifier coupled to a third node that is coupled to the third switch and a second capacitor;
- a negative output port of the second operational amplifier coupled to a fourth node that is coupled to the second capacitor and the fourth switch;
- a fifth switch coupled to a fifth node that is coupled to a second parallel array of binary-weighted linear capacitors and an eighth switch;
- a sixth switch coupled to the first voltage of common mode and a sixth node that is coupled to the second parallel array and a seventh switch;
- a negative input port of the second operational amplifier coupled to a seventh node that is coupled to the seventh switch and a fourth capacitor;
- and
- a positive output port of the second operational amplifier coupled to an eighth node that is coupled to the fourth capacitor and the eighth switch;
- wherein the first parallel array and the second capacitor are in series;
- wherein the second parallel array and the fourth capacitor are in series;
- and wherein the first parallel array and second parallel array are in parallel with each other.
9 more elements
A method, comprising:
- receiving, by a digital-to-analog converter, a digital signal;
- converting, by the digital-to-analog converter, the received digital signal to an analog signal;
- filtering, by an embedded low pass filter in the digital-to-analog converter, the analog signal to remove a signal having a frequency higher than a predetermined threshold;
- and
- outputting the filtered analog signal;
- wherein the converter comprises:
- a first switch coupled to a first node that is coupled to a fourth switch and a first parallel array of binary-weighted linear capacitors;
- a second switch coupled to a first voltage of common mode and a second node that is coupled to the first parallel array and a third switch;
- a positive input port of a second operational amplifier coupled to a third node that is coupled to the third switch and a second capacitor;
- a negative output port of the second operational amplifier coupled to a fourth node that is coupled to the second capacitor and the fourth switch;
- a fifth switch coupled to a fifth node that is coupled to a second parallel array of binary-weighted linear capacitors and an eighth switch;
- a sixth switch coupled to the first voltage of common mode and a sixth node that is coupled to the second parallel array and a seventh switch;
- a negative input port of the second operational amplifier coupled to a seventh node that is coupled to the seventh switch and a fourth capacitor;
- and
- a positive output port of the second operational amplifier coupled to an eighth node that is coupled to the fourth capacitor and the eighth switch;
- wherein the first parallel array and the second capacitor are in series;
- wherein the second parallel array and the fourth capacitor are in series;
- and wherein the first parallel array and second parallel array are in parallel with each other.
15 more elements
Dependencies are inferred from the claim text.