# US 11,115,041 B1 · Filter apparatus and control method > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,115,041 B1 - Document ID: US11115041B1 - Status: Granted - Kind: B1 - Application number: 16/837,068 - Filed: 2020-04-01 - Granted: 2021-09-07 - Earliest claimed: 2020-04-01 - Assignees: Infineon Technologies AG - Applicants: Infineon Technologies AG - Inventors: Jan Witte; Dietmar Straeussnigg - Web page: https://patentgrep.com/patent/US11115041B1 ## CPC - H03M 1/462: {Details of the control circuitry, e.g. of the successive approximation register} - H03M 3/02: Delta modulation, i.e. one-bit differential modulation {(H03M3/30 takes precedence)} - H03M 3/344: {by filtering other than the noise-shaping inherent to delta-sigma modulators, e.g. anti-aliasing} - H03M 3/378: {Testing} - H03M 3/39: {Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators (of digital delta-sigma modulators H03M7/3004)} - H03M 3/43: {the quantiser being a single bit one} - H03M 3/462: {Details relating to the decimation process (decimation filters in general H03H17/0416, H03H17/0621)} - H03M 3/498: {Variable sample rate} - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) ## Abstract A system includes an analog-to-digital converter configured to convert an analog signal generated by a digital sensor into a digital signal, and a testing apparatus configured to be enabled after the analog-to-digital converter operates in a testing mode, wherein the testing apparatus comprises a filter configured to receive the digital signal from the analog-to-digital converter, and apply a filtering process to the digital signal, a control circuit configured to terminate the filtering process after an output of the control circuit reaches a predetermined reference value, and a result register configured to receive a result generated by the filter after the control circuit terminates the filtering process. ## Claims ### Claim 1 A system comprising: an analog-to-digital converter configured to convert an analog signal generated by a digital sensor into a digital signal; and a testing apparatus configured to be enabled after the analog-to-digital converter operates in a testing mode, wherein the testing apparatus comprises: a filter configured to receive the digital signal from the analog-to-digital converter, and apply a filtering process to the digital signal, wherein as a result of applying the filtering process, the digital signal having a first sample rate is converted into a result having a second sample rate lower than the first sample rate, and wherein in the filtering process, the filter keeps accumulating values of the digital signal until the number of clock cycles reaches a predetermined reference value; a control circuit configured to terminate the filtering process after an output of the control circuit reaches the predetermined reference value; and a result register configured to receive a result generated by the filter after the control circuit terminates the filtering process. ### Claim 2 (depends on 1) The system of claim 1, wherein: the analog-to-digital converter is a delta-sigma analog-to-digital converter. ### Claim 3 (depends on 1) The system of claim 1, further comprising: an intermediate stage configured to control data transferring form the result register to an output register. ### Claim 4 (depends on 3) The system of claim 3, wherein: the digital sensor is a digital silicon microphone; the filter is an integrator; the control circuit is a counter; and the intermediate stage is a synchronization stage, and wherein the integrator, the counter, the result register, the synchronization stage and the output register form a testing circuit configured to perform a sensitivity measurement on the digital silicon microphone. ### Claim 5 (depends on 4) The system of claim 4, wherein: the testing circuit comprises a single integrator configured as a filter apparatus for converting the output signal of the analog-to-digital converter having the first sample rate into an output signal of the testing circuit having the second sample rate. ### Claim 6 (depends on 5) The system of claim 5, wherein: a ratio of the first sample rate of the output signal of the analog-to-digital converter to the second sample rate of the output signal of the testing circuit is equal to the predetermined reference value. ### Claim 7 (depends on 1) The system of claim 1, wherein: the testing apparatus and the analog-to-digital converter are disposed on a single semiconductor substrate. ### Claim 8 (depends on 1) The system of claim 1, wherein: the predetermined reference value is determined based on an oversampling rate of the analog-to-digital converter. ### Claim 9 A method comprising: configuring an analog-to-digital converter to operate in a testing mode; configuring a filter to receive a stream of bits generated by the analog-to-digital converter, and accumulate values of the stream of bits until the number of clock cycles reaches a predetermined reference value, wherein an output signal of the filter is increased by 1 in response to a digital bit of 1 from the stream of bits, and the output signal of the filter is decreased by 1 in response to a digital bit of 0 from the stream of bits; and transferring the output signal of the filter into a result register. ### Claim 10 (depends on 9) The method of claim 9, further comprising: prior to the step of configuring the filter to receive the stream of bits generated by the analog-to-digital converter, and accumulate the values of the stream of bits, resetting the filter. ### Claim 11 (depends on 9) The method of claim 9, further comprising: resetting a counter; in each clock cycle, increasing the counter by 1; and transferring the output signal of the filter into the result register after the counter reaches the predetermined reference value. ### Claim 12 (depends on 9) The method of claim 9, further comprising: transferring the output signal into the result register to an output register in response to a synchronization signal. ### Claim 13 (depends on 9) The method of claim 9, wherein: the analog-to-digital converter is a delta-sigma analog-to-digital converter having a first sample rate; and a ratio of the first sample rate of the delta-sigma analog-to-digital converter to a second sample rate of the output signal of the filter is equal to the predetermined reference value. ### Claim 14 (depends on 9) The method of claim 9, further comprising: providing a testing signal to the analog-to-digital converter; converting the testing signal into a first digital signal having a first sample rate; decimating the first digital signal by a factor equal to the predetermined reference value using the filter; and determining a sensitivity of the analog-to-digital converter based on a result from the step of decimating the first digital signal by the factor equal to the predetermined reference value using the filter. ### Claim 15 A system comprising: a delta-sigma analog-to-digital converter having inputs coupled to a digital sensor; a digital logic circuit having an input connected to the delta-sigma analog-to-digital converter, the digital logic circuit being configured to process an output signal of the delta-sigma analog-to-digital converter during a normal operation mode; and a testing circuit comprising a filter configured to receive a first stream of digital bits from an output of the delta-sigma analog-to-digital converter, and apply an integration process to the first stream of digital bits to generate a second stream of digital bits, wherein a sample rate of the second stream of digital bits is a fraction of a sample rate of the first stream of digital bits, and wherein in the integration process, the filter keeps accumulating values of the first stream of digital bits until the number of clock cycles reaches a predetermined reference value. ### Claim 16 (depends on 15) The system of claim 15, wherein the testing circuit comprises: the filter configured to receive the first stream of digital bits; a control circuit configured to terminate the integration process after an output of the control circuit reaches the predetermined reference value; a result register configured to receive a result generated by the filter after the control circuit terminates the integration process; an output register configured to receive the result from the result register; and an intermediate stage configured to control data transferring form the result register to the output register. ### Claim 17 (depends on 16) The system of claim 16, wherein the control circuit is a counter, and wherein: the counter is configured as a sample rate converter to reduce the sample rate of the first stream of digital bits. ### Claim 18 (depends on 15) The system of claim 15, wherein: a ratio of the sample rate of the first stream of digital bits to the sample rate of the second stream of digital bits is equal to an oversampling rate of the delta-sigma analog-to-digital converter. ### Claim 19 (depends on 15) The system of claim 15, wherein: the delta-sigma analog-to-digital converter, the digital logic circuit and the testing circuit are disposed on a single semiconductor substrate.