# US 11,115,038 B2 · Method for managing the startup of a phase-locked loop and corresponding integrated circuit

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- Number: US 11,115,038 B2
- Document ID: US11115038B2
- Status: Granted
- Kind: B2
- Application number: 16/923,335
- Filed: 2020-07-08
- Published: 2021-01-14
- Granted: 2021-09-07
- Earliest claimed: 2019-07-09
- Assignees: STMicroelectronics (Rousset) SAS
- Applicants: STMicroelectronics (Rousset) SAS
- Inventors: Bruno Gailhard; Laurent Truphemus; Christophe Eva
- Web page: https://patentgrep.com/patent/US11115038B2

## CPC

- H03L 7/10: for assuring initial synchronisation or for broadening the capture range
- H03L 7/199: with reset of the frequency divider or the counter, e.g. for assuring initial synchronisation
- H03L 7/0891: {the up-down pulses controlling source and sink current generators, e.g. a charge pump}
- H03L 7/099: concerning mainly the controlled oscillator of the loop
- H03L 7/1072: {by changing characteristics of the charge pump, e.g. changing the gain}
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)

## Abstract

The operation of the phase-locked loop includes a startup phase where a reference signal having a duty cycle of 50% is applied to a phase comparator of the loop. A first divider of an output signal of the voltage-controlled oscillator of the loop is reset at each first type signal edge of the reference signal. The phase comparator receives the reference signal and a feedback signal from the first divider and generates a control pulse at each second type signal edge of the reference signal that causes a control voltage of the oscillator to increase.

## Claims

### Claim 1

A method for operating a phase-locked loop (PLL) circuit, comprising:
delivering a reference signal for a phase comparator of the PLL circuit;
resetting a first divider of an output signal of a voltage-controlled oscillator of the PLL circuit at each first type signal edge of the reference signal;
outputting by the phase comparator, in response to the reference signal and a feedback signal derived from an output of said first divider, a control pulse at each second type signal edge of the reference signal; and
during startup, increasing a control voltage of the voltage-controlled oscillator in response to each control pulse by applying, in response to the control pulse, a pre-charging current to a resistive capacitive filter connected at an input of the voltage-controlled oscillator;
after startup is complete, ceasing to apply the pre-charging current to the resistive capacitive filter in response to each control pulse.

### Claim 2 (depends on 1)

The method according to claim 1, wherein delivering said reference signal comprises dividing an initial reference signal by two, and wherein said feedback signal is the output of the first divider divided by two.

### Claim 3

A method for operating a phase-locked loop (PLL) circuit, comprising:
delivering a reference signal for a phase comparator of the PLL circuit;
resetting a first divider of an output signal of a voltage-controlled oscillator of the PLL circuit at each first type signal edge of the reference signal;
outputting by the phase comparator, in response to the reference signal and a feedback signal derived from an output of said first divider, a control pulse at each second type signal edge of the reference signal; and
increasing a control voltage of the voltage-controlled oscillator in response to each control pulse;
wherein increasing the control voltage of the voltage-controlled oscillator comprises applying, in response to the control pulse, a pre-charging current to a resistive capacitive filter connected at an input of the voltage-controlled oscillator;
wherein the resistive capacitive filter comprises:
a first branch connected between said input of the voltage-controlled oscillator and ground and containing a resistive network connected in series with a first capacitor having a first capacitance, said resistive network containing a first resistor connected between said input of the voltage-controlled oscillator and an intermediate node and having a first resistance, and a second resistor connected between the intermediate node and the first capacitor and having a second resistance; and
a second branch connected between said input of the voltage-controlled oscillator and ground and containing a second capacitor having a second capacitance;
the first capacitance being equal to a value that is A times the second capacitance, and the first resistance being equal to a value that is A times the second resistance; and
wherein said pre-charging current is applied to said intermediate node.

### Claim 4 (depends on 1)

The method according to claim 1, further comprising terminating startup when a duration of the control pulse is less than a few percent of a product of a period of the output signal of the voltage-controlled oscillator and a division ratio of the first divider.

### Claim 5 (depends on 4)

The method according to claim 4, further comprising, in response to terminating startup, connecting the output of the phase comparator to a charge pump circuit configured to generate the control voltage of the voltage-controlled oscillator.

### Claim 6 (depends on 5)

The method according to claim 5, further comprising performing a last reset of the first divider on the first type signal edge of the reference signal following terminating startup.

### Claim 7 (depends on 4)

The method according to claim 4, wherein delivering said reference signal comprises dividing an initial reference signal by two, and wherein said feedback signal is the output of the first divider divided by two, and further comprising, in response to terminating startup, delivering the initial reference signal to the phase comparator, and delivering the output signal of the first divider as the feedback signal to the phase comparator.

### Claim 8 (depends on 7)

The method according to claim 7, further comprising performing a last reset of the first divider on the first type signal edge of the reference signal following terminating startup.

### Claim 9

A phase-locked loop (PLL) circuit, comprising:
a phase comparator;
a voltage-controlled oscillator;
a first divider connected between an output of the voltage-controlled oscillator and a first input of the phase comparator;
a delivery circuit configured to deliver, in a startup phase of the PLL circuit, a reference signal to a second input of the phase comparator;
a reset circuit configured, in said startup phase, to reset the first divider at each first type signal edge of the reference signal;
wherein the phase comparator is configured, in said startup phase, to deliver a control pulse at each second type signal edge of the reference signal; and
a control circuit configured to:
during the startup phase, increase a control voltage of the voltage-controlled oscillator during said control pulse by applying, in response to the control pulse, a pre-charging current to a resistive capacitive filter connected at an input of the voltage-controlled oscillator, but
after the startup phase is complete, ceasing to apply the pre-charging current to the resistive capacitive filter in response to each pulse.

### Claim 10

A phase-locked loop (PLL) circuit, comprising:
a phase comparator;
a voltage-controlled oscillator;
a first divider connected between an output of the voltage-controlled oscillator and a first input of the phase comparator;
a delivery circuit configured to deliver, in a startup phase of the PLL circuit, a reference signal to a second input of the phase comparator;
a reset circuit configured, in said startup phase, to reset the first divider at each first type signal edge of the reference signal;
wherein the phase comparator is configured, in said startup phase, to deliver a control pulse at each second type signal edge of the reference signal; and
a control circuit configured to increase a control voltage of the voltage-controlled oscillator during said control pulse;
wherein the delivery circuit comprises:
an input configured to receiving an initial reference signal;
a divide-by-two divider connected to said input; and
an output configured to deliver the initial reference signal divided by two as reference signal during said startup phase, and
another divide-by-two divider active during said startup phase and connected between the output of the first divider and the first input of the phase comparator.

### Claim 11

A phase-locked loop (PLL) circuit, comprising:
a phase comparator;
a voltage-controlled oscillator;
a first divider connected between an output of the voltage-controlled oscillator and a first input of the phase comparator;
a delivery circuit configured to deliver, in a startup phase of the PLL circuit, a reference signal to a second input of the phase comparator;
a reset circuit configured, in said startup phase, to reset the first divider at each first type signal edge of the reference signal;
wherein the phase comparator is configured, in said startup phase, to deliver a control pulse at each second type signal edge of the reference signal; and
a control circuit configured to increase a control voltage of the voltage-controlled oscillator during said control pulse;
wherein the control circuit comprises:
a current source configured to generate a pre-charging current that is selectively applied, in response to said control pulse, to a resistive capacitive filter connected at the input of the voltage-controlled oscillator;
wherein the resistive capacitive filter comprises:
a first branch connected between said input of the voltage-controlled oscillator and ground and containing a resistive network connected in series with a first capacitor having a first capacitance, said resistive network containing a first resistor connected between said input of the oscillator and an intermediate node and having a first resistance, and a second resistor connected between the intermediate node and the first capacitor and having a second resistance; and
a second branch connected between said input of the voltage-controlled oscillator and ground and containing a second capacitor having a second capacitance;
wherein the first capacitance is equal to a value A times the second capacitance, and wherein the first resistance is equal to a value A times the second resistance; and
wherein the current source is connected to said intermediate node.

### Claim 12

A phase-locked loop (PLL) circuit, comprising:
a phase comparator;
a voltage-controlled oscillator;
a first divider connected between an output of the voltage-controlled oscillator and a first input of the phase comparator;
a delivery circuit configured to deliver, in a startup phase of the PLL circuit, a reference signal to a second input of the phase comparator;
a reset circuit configured, in said startup phase, to reset the first divider at each first type signal edge of the reference signal;
wherein the phase comparator is configured, in said startup phase, to deliver a control pulse at each second type signal edge of the reference signal;
a control circuit configured to increase a control voltage of the voltage-controlled oscillator during said control pulse; and
a detection circuit configured to detect an end of the startup phase.

### Claim 13 (depends on 12)

The circuit according to claim 12, wherein the detection circuit senses one of a duration of the control pulse and a type of pulse signal delivered by the phase comparator in order to detect end of the startup phase.

### Claim 14 (depends on 13)

The circuit according to claim 13, wherein the detection circuit is further configured generate a signal indicating the end of the startup phase when the duration of the control pulse is less than a few percent of a product of a period of the output signal of the voltage-controlled oscillator and a division ratio of the first divider.

### Claim 15 (depends on 12)

The circuit according to claim 12, further comprising a switching circuit configured, when the startup phase has ended, to connect the output of the phase comparator to a charge pump circuit which generates the control voltage of the voltage-controlled oscillator.

### Claim 16 (depends on 15)

The circuit according to claim 15, wherein the reset circuit is configured, when the startup phase has ended, to perform a last reset of the first divider on the first type signal edge of the reference signal following the end of the startup phase.

### Claim 17 (depends on 12)

The circuit according to claim 12, wherein the delivery circuit comprises:
an input configured to receiving an initial reference signal;
a divide-by-two divider connected to said input; and
an output configured to deliver the initial reference signal divided by two as reference signal during said startup phase, and
further comprising another divide-by-two divider active during said startup phase and connected between the output of the first divider and the first input of the phase comparator;
wherein the delivery circuit is configured, when the startup phase has ended, to deliver the initial reference signal to the phase comparator;
a control circuit configured to deactivate said other divide-by-two divider, such that a feedback signal delivered to the phase comparator is the output signal of the first divider.

### Claim 18 (depends on 17)

The circuit according to claim 17, wherein the reset circuit is configured, when the startup phase has ended, to perform a last reset of the first divider on the first type signal edge of the reference signal following the end of the startup phase.

### Claim 19 (depends on 3)

The method according to claim 3, further comprising terminating startup when a duration of the control pulse is less than a few percent of a product of a period of the output signal of the voltage-controlled oscillator and a division ratio of the first divider.

### Claim 20 (depends on 19)

The method according to claim 19, further comprising, in response to terminating startup, connecting the output of the phase comparator to a charge pump circuit configured to generate the control voltage of the voltage-controlled oscillator.

### Claim 21 (depends on 20)

The method according to claim 20, further comprising performing a last reset of the first divider on the first type signal edge of the reference signal following terminating startup.

### Claim 22 (depends on 19)

The method according to claim 19, wherein delivering said reference signal comprises dividing an initial reference signal by two, and wherein said feedback signal is the output of the first divider divided by two, and further comprising, in response to terminating startup, delivering the initial reference signal to the phase comparator, and delivering the output signal of the first divider as the feedback signal to the phase comparator.

### Claim 23 (depends on 22)

The method according to claim 22, further comprising performing a last reset of the first divider on the first type signal edge of the reference signal following terminating startup.

### Claim 24 (depends on 11)

The circuit according to claim 11, further comprising a detection circuit configured to detect an end of the startup phase.

### Claim 25 (depends on 24)

The circuit according to claim 24, wherein the detection circuit senses one of a duration of the control pulse and a type of pulse signal delivered by the phase comparator in order to detect end of the startup phase.

### Claim 26 (depends on 25)

The circuit according to claim 25, wherein the detection circuit is further configured generate a signal indicating the end of the startup phase when the duration of the control pulse is less than a few percent of a product of a period of the output signal of the voltage-controlled oscillator and a division ratio of the first divider.

### Claim 27 (depends on 24)

The circuit according to claim 24, further comprising a switching circuit configured, when the startup phase has ended, to connect the output of the phase comparator to a charge pump circuit which generates the control voltage of the voltage-controlled oscillator.

### Claim 28 (depends on 27)

The circuit according to claim 27, wherein the reset circuit is configured, when the startup phase has ended, to perform a last reset of the first divider on the first type signal edge of the reference signal following the end of the startup phase.

### Claim 29 (depends on 24)

The circuit according to claim 24, wherein the delivery circuit comprises:
an input configured to receiving an initial reference signal;
a divide-by-two divider connected to said input; and
an output configured to deliver the initial reference signal divided by two as reference signal during said startup phase, and
further comprising another divide-by-two divider active during said startup phase and connected between the output of the first divider and the first input of the phase comparator;
wherein the delivery circuit is configured, when the startup phase has ended, to deliver the initial reference signal to the phase comparator;
a control circuit configured to deactivate said other divide-by-two divider, such that a feedback signal delivered to the phase comparator is the output signal of the first divider.

### Claim 30 (depends on 29)

The circuit according to claim 29, wherein the reset circuit is configured, when the startup phase has ended, to perform a last reset of the first divider on the first type signal edge of the reference signal following the end of the startup phase.

### Claim 31 (depends on 9)

The circuit according to claim 9, wherein the delivery circuit comprises:
an input configured to receiving an initial reference signal;
a divide-by-two divider connected to said input; and
an output configured to deliver the initial reference signal divided by two as reference signal during said startup phase, and
further comprising another divide-by-two divider active during said startup phase and connected between the output of the first divider and the first input of the phase comparator.

### Claim 32 (depends on 9)

The circuit according to claim 9, wherein the resistive capacitive filter comprises:
a first branch connected between said input of the voltage-controlled oscillator and ground and containing a resistive network connected in series with a first capacitor having a first capacitance, said resistive network containing a first resistor connected between said input of the oscillator and an intermediate node and having a first resistance, and a second resistor connected between the intermediate node and the first capacitor and having a second resistance; and
a second branch connected between said input of the voltage-controlled oscillator and ground and containing a second capacitor having a second capacitance;
wherein the first capacitance is equal to a value A times the second capacitance, and wherein the first resistance is equal to a value A times the second resistance; and
wherein a current source is connected to said intermediate node to deliver the pre-charge current.

### Claim 33 (depends on 9)

The circuit according to claim 9, further comprising a detection circuit configured to detect an end of the startup phase.

### Claim 34 (depends on 33)

The circuit according to claim 33, wherein the detection circuit senses one of a duration of the control pulse and a type of pulse signal delivered by the phase comparator in order to detect end of the startup phase.

### Claim 35 (depends on 34)

The circuit according to claim 34, wherein the detection circuit is further configured generate a signal indicating the end of the startup phase when the duration of the control pulse is less than a few percent of a product of a period of the output signal of the voltage-controlled oscillator and a division ratio of the first divider.

### Claim 36 (depends on 33)

The circuit according to claim 33, further comprising a switching circuit configured, when the startup phase has ended, to connect the output of the phase comparator to a charge pump circuit which generates the control voltage of the voltage-controlled oscillator.

### Claim 37 (depends on 36)

The circuit according to claim 36, wherein the reset circuit is configured, when the startup phase has ended, to perform a last reset of the first divider on the first type signal edge of the reference signal following the end of the startup phase.

### Claim 38 (depends on 33)

The circuit according to claim 33, wherein the delivery circuit comprises:
an input configured to receiving an initial reference signal;
a divide-by-two divider connected to said input; and
an output configured to deliver the initial reference signal divided by two as reference signal during said startup phase, and
further comprising another divide-by-two divider active during said startup phase and connected between the output of the first divider and the first input of the phase comparator;
wherein the delivery circuit is configured, when the startup phase has ended, to deliver the initial reference signal to the phase comparator;
a control circuit configured to deactivate said other divide-by-two divider, such that a feedback signal delivered to the phase comparator is the output signal of the first divider.

### Claim 39 (depends on 38)

The circuit according to claim 38, wherein the reset circuit is configured, when the startup phase has ended, to perform a last reset of the first divider on the first type signal edge of the reference signal following the end of the startup phase.

### Claim 40 (depends on 10)

The circuit according to claim 10, wherein the control circuit comprises:
a current source configured to generate a pre-charging current that is selectively applied, in response to said control pulse, to a resistive capacitive filter connected at the input of the voltage-controlled oscillator.

### Claim 41 (depends on 40)

The circuit according to claim 40, wherein the resistive capacitive filter comprises:
a first branch connected between said input of the voltage-controlled oscillator and ground and containing a resistive network connected in series with a first capacitor having a first capacitance, said resistive network containing a first resistor connected between said input of the oscillator and an intermediate node and having a first resistance, and a second resistor connected between the intermediate node and the first capacitor and having a second resistance; and
a second branch connected between said input of the voltage-controlled oscillator and ground and containing a second capacitor having a second capacitance;
wherein the first capacitance is equal to a value A times the second capacitance, and wherein the first resistance is equal to a value A times the second resistance; and
wherein the current source is connected to said intermediate node.

### Claim 42 (depends on 10)

The circuit according to claim 10, further comprising a detection circuit configured to detect an end of the startup phase.

### Claim 43 (depends on 42)

The circuit according to claim 42, wherein the detection circuit senses one of a duration of the control pulse and a type of pulse signal delivered by the phase comparator in order to detect end of the startup phase.

### Claim 44 (depends on 43)

The circuit according to claim 43, wherein the detection circuit is further configured generate a signal indicating the end of the startup phase when the duration of the control pulse is less than a few percent of a product of a period of the output signal of the voltage-controlled oscillator and a division ratio of the first divider.

### Claim 45 (depends on 42)

The circuit according to claim 42, further comprising a switching circuit configured, when the startup phase has ended, to connect the output of the phase comparator to a charge pump circuit which generates the control voltage of the voltage-controlled oscillator.

### Claim 46 (depends on 45)

The circuit according to claim 45, wherein the reset circuit is configured, when the startup phase has ended, to perform a last reset of the first divider on the first type signal edge of the reference signal following the end of the startup phase.

### Claim 47 (depends on 42)

The circuit according to claim 42, wherein the delivery circuit comprises:
an input configured to receiving an initial reference signal;
a divide-by-two divider connected to said input; and
an output configured to deliver the initial reference signal divided by two as reference signal during said startup phase, and
further comprising another divide-by-two divider active during said startup phase and connected between the output of the first divider and the first input of the phase comparator;
wherein the delivery circuit is configured, when the startup phase has ended, to deliver the initial reference signal to the phase comparator;
a control circuit configured to deactivate said other divide-by-two divider, such that a feedback signal delivered to the phase comparator is the output signal of the first divider.

### Claim 48 (depends on 47)

The circuit according to claim 47, wherein the reset circuit is configured, when the startup phase has ended, to perform a last reset of the first divider on the first type signal edge of the reference signal following the end of the startup phase.