Spur cancelation in phase-locked loops using a reconfigurable digital-to-time converter

A method, comprising:

• generating an oscillator signal by an oscillator circuit;
• dividing a frequency of the oscillator signal using a divisor to generate a plurality of divider output signals, wherein a frequency of a given one of the plurality of divider output signals is a fractional quotient of a frequency of the oscillator signal;
• selecting a particular divider output signal of the plurality of divider output signals using an accumulated phase residue associated with dividing the frequency of the oscillator signal;
• delaying, using the accumulated phase residue, the particular divider output signal to generate a feedback signal;
• and
• adjusting a frequency of the oscillator signal using results of a comparison of the feedback signal and a reference signal.

An apparatus, comprising:

• a voltage regulator circuit configured to generate a particular voltage level on a regulated power supply node;
• a power delivery network including a plurality of resistors, wherein the power delivery network is coupled to the regulated power supply node and configured to generate, using a voltage level of the regulated power supply node, a plurality of local power supply signals on corresponding ones of a plurality of local supply nodes, wherein two adjacent local supply nodes of the plurality of local supply nodes are isolated from one another by a particular resistor of the plurality of resistors;
• and
• a delay line circuit including a plurality of delay stages coupled together in a serial fashion, wherein the delay line circuit is configured to delay an input signal to generate a plurality of delayed signals, wherein the plurality of delay stages is coupled to corresponding ones of the plurality of local supply node, and wherein an initial delay stage is coupled to the input signal, and a last delay stage is coupled to the regulated power supply node.