# US 11,115,035 B2 · Semiconductor devices

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- Number: US 11,115,035 B2
- Document ID: US11115035B2
- Status: Granted
- Kind: B2
- Application number: 16/970,750
- Filed: 2019-06-05
- Published: 2021-04-01
- Granted: 2021-09-07
- Earliest claimed: 2018-06-15
- Assignees: Mitsubishi Heavy Industries, Ltd.
- Applicants: Mitsubishi Heavy Industries, Ltd.
- Inventors: Takanori Narita; Daisuke Matsuura; Shigeru Ishii; Daisuke Kobayashi; Kazuyuki Hirose; Osamu Kawasaki
- Web page: https://patentgrep.com/patent/US11115035B2

## CPC

- H03K 3/023: by the use of differential amplifiers or comparators, with internal or external positive feedback
- H03L 7/093: using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence)
- G06F 1/04: Generating or distributing clock signals or signals derived directly therefrom
- H03H 11/26: Time-delay networks
- H03K 5/00: Manipulating of pulses not covered by one of the other main groups of this subclass (circuits with regenerative action H03K3/00, H03K4/00; by the use of non-linear magnetic or dielectric devices H03K3/45)
- H03K 5/1252: Suppression or limitation of noise or interference (specially adapted for transmission systems H04B15/00, H04L25/08)
- H03K 5/131: Digitally controlled
- H03K 19/003: Modifications for increasing the reliability {for protection}
- H03L 7/23: with pulse counters or frequency dividers
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H03H: IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS (waveguides, resonators, lines or other devices of the waveguide type H01P)

## Abstract

A semiconductor device includes first to N-th PLL circuits configured to operate in synchronization with a common reference clock signal to output first to N-th clock signals, respectively; a majority circuit that performs a majority operation on the first to N-th clock signals to generate a majority clock signal; and a filter circuit to which the majority clock signal is provided, the filter circuit operating as a low-pass filter to output an output clock signal. N is an odd number of three or more.

## Claims

### Claim 1

A semiconductor device, comprising:
first to N-th PLL circuits configured to operate in synchronization with a common reference clock signal to output first to N-th clock signals, respectively, for N being an odd number of three or more;
a majority circuit that performs a majority operation on the first to N-th clock signals to generate a majority clock signal; and
a filter circuit to which the majority clock signal is provided, the filter circuit operating as a low-pass filter to output an output clock signal,
wherein the filter circuit comprises:
a first RS flipflop that has a reset terminal to which the majority clock signal or an inverted signal of the majority clock signal is provided; and
a first delay circuit that supplies a first delay signal to a set terminal of the first RS flipflop, the first delay signal being generated by delaying the majority clock signal,
wherein the output clock signal is generated in response to a signal output from a data output of the first RS flipflop.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein the filter circuit further comprises a first inverter to which the majority clock signal is provided, and
wherein an output signal of the first inverter is provided to the reset terminal of the first RS flipflop.

### Claim 3 (depends on 2)

The semiconductor device according to claim 2, wherein the first delay circuit is configured to have a variable delay time.

### Claim 4 (depends on 3)

The semiconductor device according to claim 3, further comprising a delay setting register storing delay setting data that specifies the delay time.

### Claim 5 (depends on 3)

The semiconductor device according to claim 3, further comprising a delay setting circuit that sets the delay time of the first delay circuit based on PLL setting data that specifies an oscillation frequency of the first to N-th PLL circuits.

### Claim 6 (depends on 1)

The semiconductor device according to claim 1, wherein the first delay circuit is configured to have a variable delay time.

### Claim 7 (depends on 6)

The semiconductor device according to claim 6, further comprising a delay setting register storing delay setting data that specifies the delay time.

### Claim 8 (depends on 6)

The semiconductor device according to claim 6, further comprising a delay setting circuit that sets the delay time of the first delay circuit based on PLL setting data that specifies an oscillation frequency of the first to N-th PLL circuits.

### Claim 9

A semiconductor device, comprising:
first to N-th PLL circuits configured to operate in synchronization with a common reference clock signal to output first to N-th clock signals, respectively, for N being an odd number of three or more;
a majority circuit that performs a majority operation on the first to N-th clock signals to generate a majority clock signal; and
a filter circuit to which the majority clock signal is provided, the filter circuit operating as a low-pass filter to output an output clock signal,
wherein the filter circuit comprises:
a first filter to which the majority clock signal is provided;
a second inverter to which an output signal of the first filter is provided; and
a second filter to which an output signal of the second inverter is provided,
wherein the first filter is configured to output a clock signal with a duty ratio different from that of the majority clock signal, and
wherein the first filter and the second filter have the same configuration.

### Claim 10

A semiconductor device, comprising:
first to N-th PLL circuits configured to operate in synchronization with a common reference clock signal to output first to N-th clock signals, respectively, for N being an odd number of three or more;
a majority circuit that performs a majority operation on the first to N-th clock signals to generate a majority clock signal; and
a filter circuit to which the majority clock signal is provided, the filter circuit operating as a low-pass filter to output an output clock signal,
wherein the filter circuit comprises:
a first filter to which the majority clock signal is provided;
a second inverter to which an output signal of the first filter is provided; and
a second filter to which an output signal of the second inverter is provided,
wherein the first filter comprises:
a third inverter to which the majority clock signal is provided;
a first RS flipflop; and
a first delay circuit that supplies a first delay signal to a set terminal of the first RS flipflop, the first delay signal being generated by delaying the majority clock signal;
wherein the second filter comprises:
a fourth inverter to which an output signal of the second inverter is provided;
a second RS flipflop; and
a second delay circuit that supplies a second delay signal to a set terminal of the second RS flipflop, the second delay signal being generated by delaying the output signal of the second inverter.

### Claim 11 (depends on 10)

The semiconductor device according to claim 10, wherein the first delay circuit and the second delay circuit are configured to have the same delay time, the delay time being variable.

### Claim 12 (depends on 11)

The semiconductor device according to claim 11, further comprising a delay setting circuit that sets the delay time of the first delay circuit and the second delay circuit based on PLL setting data that specifies an oscillation frequency of the first to N-th PLL circuits.