# US 11,115,034 B2 · Signal detection circuit and signal detection method

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- Number: US 11,115,034 B2
- Document ID: US11115034B2
- Status: Granted
- Kind: B2
- Application number: 16/993,275
- Filed: 2020-08-14
- Published: 2021-04-01
- Granted: 2021-09-07
- Earliest claimed: 2019-09-26
- Assignees: Realtek Semiconductor Corp.
- Applicants: Realtek Semiconductor Corp.
- Inventors: Bing-Hung Chen
- Web page: https://patentgrep.com/patent/US11115034B2

## CPC

- H03L 7/091: the phase or frequency detector using a sampling device (H03L7/087 takes precedence)
- H03K 3/356: Bistable circuits
- H03L 7/0807: {concerning mainly a recovery circuit for the reference signal}
- H03L 7/183: a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number {(H03L7/1806 takes precedence)}
- G11C 7/1084: {Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load}
- G11C 7/1087: {Data input latches}
- G11C 27/02: Sample-and-hold arrangements (G11C27/04 takes precedence)
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

The present invention provides a signal detection circuit, wherein the signal detection circuit includes a sampling circuit and a determination circuit. In the operations of the signal detection circuit, the sampling circuit uses a plurality of clock signals to sample an input signal to generate a sampling result, wherein the plurality of clock signals have different phases, and frequencies of the plurality of clock signals are lower than a frequency of the input signal. The determination circuit refers to the sampling result to determine if the input signal comprises valid data, so as to determine if the input signal comes from outside a chip, wherein the chip includes the signal detection circuit.

## Claims

### Claim 1

A signal detection circuit, comprising:
a sampling circuit, configured to use a plurality of clock signals to sample an input signal to generate a sampling result, wherein the plurality of clock signals have different phases, and frequencies of the plurality of clock signals are lower than a frequency of the input signal; and
a determination circuit, coupled to the sampling circuit, configured to refer to the sampling result to determine if the input signal comprises valid data, so as to determine if the input signal comes from outside a chip, wherein the chip comprises the signal detection circuit;
a clock signal generating circuit, configured to generate the plurality of clock signals having different phases according to a reference clock signal, wherein the clock signal generating circuit sequentially outputs the plurality of clock signals having different phases to the sampling circuit, for the sampling circuit to use only one of the plurality of clock signals to sample the input signal at a time.

### Claim 2 (depends on 1)

The signal detection circuit of claim 1, wherein the plurality of clock signals comprise a first clock signal and a second clock signal, a phase difference between the first clock signal and the second clock signal is greater than a transition time of the input signal, and the phase difference between the first clock signal and the second clock signal is less than a difference between a period of the input signal and the transition time.

### Claim 3 (depends on 2)

The signal detection circuit of claim 2, wherein the plurality of clock signals further comprise a third clock signal, a difference between a first phase different and a second phase difference is greater than the transition time of the input signal, and the difference between the first phase different and the second phase difference is less than the difference between the period of the input signal and the transition time, wherein the first phase difference is the phase difference between the first clock signal and the second clock signal, and the second phase difference is a phase difference between the second clock signal and the third clock signal.

### Claim 4 (depends on 1)

The signal detection circuit of claim 1, wherein the sampling circuit comprises latches to use the plurality of clock signals to sample the input signal to generate the sampling result.

### Claim 5 (depends on 4)

The signal detection circuit of claim 4, wherein the sampling circuit comprises:
a first latching-type sampling circuit, configured to use the plurality of clock signals to sample the input signal to generate the sampling result.

### Claim 6 (depends on 5)

The signal detection circuit of claim 5, wherein the input signal is a differential signal comprising a first input signal and a second input signal, the first latching-type sampling circuit is configured to use the plurality of clock signals to sample the first input signal to generate a first sampled signal; and the sampling circuit further comprises:
a second latching-type sampling circuit, configured to use the plurality of clock signals to sample the second input signal to generate a second sampled result; and
an output circuit, coupled to the first latching-type sampling circuit and the second latching-type sampling circuit, configured to generate the sampling result according to the first sampled result and the second sampled result.

### Claim 7

A signal detection method, comprising:
using a sampling circuit to use a plurality of clock signals to sample an input signal to generate a sampling result, wherein the plurality of clock signals have different phases, and frequencies of the plurality of clock signals are lower than a frequency of the input signal; and
referring to the sampling result to determine if the input signal comprises valid data, so as to determine if the input signal comes from outside a chip;
using a clock signal generating circuit to generate the plurality of clock signals having different phases according to a reference clock signal, wherein the clock signal generating circuit sequentially outputs the plurality of clock signals having different phases to the sampling circuit, for the sampling circuit to use only one of the plurality of clock signals to sample the input signal at a time.

### Claim 8 (depends on 7)

The signal detection method of claim 7, wherein the plurality of clock signals comprise a first clock signal and a second clock signal, a phase difference between the first clock signal and the second clock signal is greater than a transition time of the input signal, and the phase difference between the first clock signal and the second clock signal is less than a difference between a period of the input signal and the transition time.

### Claim 9 (depends on 8)

The signal detection method of claim 8, wherein the plurality of clock signals further comprise a third clock signal, a difference between a first phase different and a second phase difference is greater than the transition time of the input signal, and the difference between the first phase different and the second phase difference is less than the difference between the period of the input signal and the transition time, wherein the first phase difference is the phase difference between the first clock signal and the second clock signal, and the second phase difference is a phase difference between the second clock signal and the third clock signal.

### Claim 10 (depends on 7)

The signal detection method of claim 7, wherein the step of using the plurality of clock signals to sample the input signal to generate the sampling result is performed by a sampling circuit comprising latches.

### Claim 11 (depends on 10)

The signal detection method of claim 10, wherein the input signal is a differential signal comprising a first input signal and a second input signal, and the step of using the plurality of clock signals to sample the input signal to generate the sampling result comprises:
using the plurality of clock signals to sample the first input signal to generate a first sampled result;
using the plurality of clock signals to sample the second input signal to generate a second sampled result; and
generating the sampling result according to the first sampled result and the second sampled result.

### Claim 12 (depends on 1)

The signal detection circuit of claim 1, wherein the clock signal generating circuit comprises:
an oscillator, configured to generate the reference clock signal;
a plurality of delay circuits, configured to generate the plurality of clock signals having different phases; and
a multiplexer, coupled to the plurality of delay circuits, configured to receive the plurality of clock signals and sequentially output the plurality of clock signals to the sampling circuit.

### Claim 13 (depends on 12)

The signal detection circuit of claim 12, wherein the plurality of delay circuits are connected in series, and output signals of a portion of the delay circuits serve as the plurality of clock signals.

### Claim 14 (depends on 7)

The signal detection method of claim 7, wherein the clock signal generating circuit comprises:
an oscillator, configured to generate the reference clock signal;
a plurality of delay circuits, configured to generate the plurality of clock signals having different phases; and
a multiplexer, coupled to the plurality of delay circuits, configured to receive the plurality of clock signals and sequentially output the plurality of clock signals to the sampling circuit.

### Claim 15 (depends on 14)

The signal detection method of claim 14, wherein the plurality of delay circuits are connected in series, and output signals of a portion of the delay circuits serve as the plurality of clock signals.