Universal transceiver container
AssigneeIntel Corporation
InventorsSergey Y. Shumarayev, David W. Mendel, Joel Martinez, Curt Wortman
Life of this patent
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Abstract
The present disclosure relates to modular transceiver-based network circuitries that may include internal configurable interfaces or gaskets. The configurable gaskets may facilitate integration of the network circuitries in electronic devices by providing a transparent interface to processing circuitries coupled to the network circuitries. Moreover, the configurable gaskets may also have a floorplan layout (e.g., a chiplet layout) that may facilitate coupling of multiple network circuitries to a single processing circuitry, in a modular manner.
Claims24
A network adaptor, comprising:
- a plurality of physical coding sublayer (PCS) lanes;
- a protocol intellectual property (IP) block configured to implement a first protocol;
- a physical medium attachment (PMA) gasket circuitry configured to couple the PCS lanes to the protocol IP block;
- an interconnect bus interface configured to provide connectivity between the network adaptor to an interconnect bus;
- and
- a digital gasket circuitry configured to couple the protocol IP block to the interconnect bus interface.
An electronic device comprising:
- processing circuitry comprising an interconnect bus interface;
- and
- network circuitry coupled to the processing circuitry via the interconnect bus interface, wherein the network circuitry comprises:
- a first plurality of physical coding sublayer (PCS) lanes;
- a first protocol intellectual property (IP) block configured to implement a protocol;
- a first physical medium attachment (PMA) gasket circuitry configured to couple the first plurality of PCS lanes to the first protocol IP block;
- an interconnect bus interface configured to provide connectivity between the network circuitry to an interconnect bus;
- a digital gasket circuitry configured to couple the first protocol IP block to the interconnect bus interface;
- a high-speed serial interface (HSSI) circuitry configured to exchange control and status signals from the interconnect bus interface;
- a digital control gasket circuitry configured to couple the HSSI circuitry to the first protocol IP block;
- and
- an analog control gasket circuitry configured to couple the HSSI circuitry to the PCS lanes.
A method to configure a network interface comprising a plurality of transceivers, a protocol intellectual property (IP) block, a physical medium attachment (PMA) gasket, and a digital gasket, the method comprising:
- receiving a protocol specification for an interconnect bus;
- configuring the digital gasket that couples the protocol IP block to the interconnect bus based on the received protocol specification and a protocol of the protocol IP block;
- determining a PMA coding based on the received protocol specification;
- and
- configuring the PMA gasket based on the PMA coding, wherein configuring the PMA gasket comprises mapping at least one physical coding sublayer (PCS) lane of a plurality of PCS lanes to a logical lane of the protocol IP block.
Dependencies are inferred from the claim text.