# US 11,115,024 B2 · Integrated circuit, test method for testing integrated circuit, and electronic device

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- Number: US 11,115,024 B2
- Document ID: US11115024B2
- Status: Granted
- Kind: B2
- Application number: 16/816,528
- Filed: 2020-03-12
- Published: 2021-03-18
- Granted: 2021-09-07
- Earliest claimed: 2019-09-12
- Assignees: Kabushiki Kaisha Toshiba
- Applicants: Kabushiki Kaisha Toshiba
- Inventors: Masato Oda; Shinichi Yasuda
- Web page: https://patentgrep.com/patent/US11115024B2

## CPC

- H03K 19/17728: Reconfigurable logic blocks, e.g. lookup tables
- G01R 31/31707: {Test strategies (methods for generation of test sequences G01R31/318371)}
- G01R 31/31713: {Input or output interfaces for test, e.g. test pins, buffers (for scan test G01R31/318572)}
- G11C 11/1655: {Bit-line or column circuits}
- G11C 11/1657: {Word-line or row circuits}
- G11C 13/0026: {Bit-line or column circuits}
- G11C 13/0028: {Word-line or row circuits}
- G11C 17/16: using electrically-fusible links
- G11C 17/18: Auxiliary circuits, e.g. for writing into memory
- G11C 29/027: {in fuses}
- G11C 29/10: Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns
- G11C 29/14: Implementation of control logic, e.g. test mode decoders
- G11C 29/32: Serial access; Scan testing
- G11C 29/36: Data generation devices, e.g. data inverters
- G11C 29/54: Arrangements for designing test circuits, e.g. design for test [DFT] tools
- H03K 17/693: Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors (logic circuits H03K19/00; code converters H03M5/00, H03M7/00)
- H03K 17/80: using non-linear magnetic devices; using non-linear dielectric devices {(H03K17/95, H03K17/97 take precedence)}
- H03K 19/1735: {by wiring, e.g. uncommitted logic arrays}
- H03K 19/1737: {using multiplexers (H03K19/1738 takes precedence)}
- H03K 19/1776: for memories
- G11C 7/1006: {Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor}
- G11C 11/1675: {Writing or programming circuits or methods}
- G11C 13/0069: {Writing or programming circuits or methods}
- G11C 29/56004: {Pattern generation}
- G11C 2029/3202: {Scan chain}
- G11C 2029/3602: {Pattern generator}
- G11C 2213/77: Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

An integrated circuit of an embodiment includes: a logic circuit; and a switch circuit, the logic circuit including: a first memory; a look-up table circuit having a first output terminal; a first selection circuit having a first input terminal connecting to the first output terminal, a second input terminal receiving scan input data, and a second output terminal, the first selection circuit selecting one of the first and second input terminals and connect the selected one to the second output terminal; a flip-flop having a third input terminal connected to the second and third output terminals; and a second selection circuit having a fourth and fifth input terminals connected to the third output terminal and the first output terminal respectively, and a fourth output terminal, the second selection circuit selecting one of the fourth and fifth input terminals and connect the selected one to the fourth output terminal.

## Claims

### Claim 1

An integrated circuit comprising:
a first logic circuit configured to first implement logic information; and
a first switch circuit configured to enable switching of wiring lines connected to the first logic circuit,
the first logic circuit comprising:
a first memory;
a first look-up table circuit having a first output terminal for outputting data stored in the first memory based on a first input signal;
a first selection circuit having a first input terminal to which the first output terminal is connected, a second input terminal that receives scan input data, and a second output terminal, the first selection circuit being configured to select one of the first input terminal and the second input terminal based on a scan enable signal and connect selected one of the first input terminal and the second input terminal to the second output terminal;
a first flip-flop having a third input terminal connected to the second output terminal and a third output terminal; and
a second selection circuit having a fourth input terminal connected to the third output terminal, a fifth input terminal connected to the first output terminal, and a fourth output terminal, the second selection circuit being configured to select one of the fourth input terminal and the fifth input terminal based on an enable signal and connect selected one of the fourth input terminal and the fifth input terminal to the fourth output terminal,
the first switch circuit performing the switching of the wiring lines in response to signals from the third output terminal and the fourth output terminal.

### Claim 2 (depends on 1)

The integrated circuit according to claim 1, wherein the first switch circuit includes a second memory, to which data can be written only once, and performs the switching of the wiring lines using the data stored in the second memory.

### Claim 3 (depends on 2)

The integrated circuit according to claim 2, wherein the second memory includes a first wiring line, a second wiring line intersecting with the first wiring line, and a switching element disposed in an intersection region between the first wiring line and the second wiring line, the switching element having a first terminal connected to the first wiring line and a second terminal connected to the second wiring line.

### Claim 4 (depends on 3)

The integrated circuit according to claim 3, wherein the switching element is an anti-fuse element or a resistive change element.

### Claim 5 (depends on 1)

The integrated circuit according to claim 1, further comprising: a second logic circuit configured to second implement logic information; and a second switch circuit configured to enable switching of wiring lines connected to the second logic circuit,
the second logic circuit comprising:
a second memory;
a second look-up table circuit having a five output terminal for outputting data stored in the second memory based on a second input signal;
a third selection circuit having a sixth input terminal to which the five output terminal is connected, a seventh input terminal to which the third output terminal is connected, and a sixth output terminal, the third selection circuit being configured to select one of the sixth input terminal and the seventh input terminal based on the scan enable signal and connect selected one of the sixth input terminal and the seventh input terminal to the sixth output terminal;
a second flip-flop having an eighth input terminal connected to the sixth output terminal and a seventh output terminal; and
a fourth selection circuit having a ninth input terminal connected to the seventh output terminal, a tenth input terminal connected to the five output terminal, and an eighth output terminal, the fourth selection circuit being configured to select one of the ninth input terminal and the tenth input terminal based on the enable signal and connect selected one of the ninth input terminal and the tenth input terminal to the eighth output terminal,
the second switch circuit performing the switching of the wiring lines in response to signals from the third output terminal and the fourth output terminal.

### Claim 6 (depends on 5)

The integrated circuit according to claim 5, wherein the second switch circuit includes a third memory, to which data can be written only once, and performs the switching of the wiring lines using the data stored in the third memory.

### Claim 7 (depends on 1)

A test method for testing a circuit in which a plurality of integrated circuits according to claim 1 are arranged in an array form, and the third output terminal of the flip-flop included in one of adjacent logic circuits is connected to the second input terminal of the first selection circuit included in the other of the adjacent logic circuits,
the test method comprising:
expressing the look-up table circuit as logic gates using a truth table of the look-up table circuit of the logic circuit and arrangement information of the integrated circuit;
forming a scan chain using the arrangement information;
generating a test pattern by means of an automatic test pattern generator based on the arrangement information;
generating a modified test pattern in which predetermined data is given to the flip-flop of the logic circuit of the integrated circuit, which is not included in the scan chain of the integrated circuits;
causing the integrated circuit to be in a scan mode using a scan enable signal; and
performing a test using the modified test pattern as scan input data.

### Claim 8 (depends on 7)

The test method according to claim 7, wherein the switch circuit includes a second memory, to which data can be written only once, and performs the switching of the wiring lines using the data stored in the second memory.

### Claim 9 (depends on 8)

The test method according to claim 8, wherein the second memory includes a first wiring line, a second wiring line intersecting with the first wiring line, and a switching element disposed in an intersection region between the first wiring line and the second wiring line, the switching element having a first terminal connected to the first wiring line and a second terminal connected to the second wiring line.

### Claim 10 (depends on 9)

The test method according to claim 9, wherein the switching element is an anti-fuse element or a resistive change element.

### Claim 11 (depends on 1)

An electronic device comprising:
the integrated circuit according to claim 1;
a third memory configured to store a program; and
a processor configured to perform a process on the integrated circuit according to the program stored in the third memory.

### Claim 12 (depends on 11)

The electronic device according to claim 11, wherein the switch circuit includes a second memory, to which data can be written only once, and performs the switching of the wiring lines using the data stored in the second memory.

### Claim 13 (depends on 12)

The electronic device according to claim 12, wherein the second memory includes a first wiring line, a second wiring line intersecting with the first wiring line, and a switching element disposed in an intersection region between the first wiring line and the second wiring line, the switching element having a first terminal connected to the first wiring line and a second terminal connected to the second wiring line.

### Claim 14 (depends on 13)

The electronic device according to claim 13, wherein the switching element is an anti-fuse element or a resistive change element.