# US 11,115,015 B2 · Device including multi-mode input pad > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,115,015 B2 - Document ID: US11115015B2 - Status: Granted - Kind: B2 - Application number: 16/694,142 - Filed: 2019-11-25 - Published: 2020-03-19 - Granted: 2021-09-07 - Earliest claimed: 2015-09-11 - Assignees: Skyworks Solutions, Inc. - Applicants: Skyworks Solutions, Inc. - Inventors: Bo Zhou; Guillaume Alexandre Blin - Web page: https://patentgrep.com/patent/US11115015B2 ## CPC - H03K 5/24: the characteristic being amplitude - G06F 13/00: Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units (interface circuits for specific input/output devices G06F3/00 {; multiprogram control therefor G06F9/46}; multiprocessor systems G06F15/16 ) - H03K 19/0175: Coupling arrangements; Interface arrangements (interface arrangements for digital computers G06F3/00, G06F13/00) - H04B 1/38: Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H04B: TRANSMISSION ## Abstract A circuit component has an address determined from a voltage level applied to a single electrical contact of the circuit component. The circuit component is configured to be assigned one of at least three unique addresses and to select from among the at least three unique addresses based on the voltage level. ## Claims ### Claim 1 A circuit component having a multi-bit binary address, the multi-bit binary address determined from a voltage level applied to a single electrical contact of the circuit component, the circuit component configured to be assigned one of at least three unique multi-bit binary addresses and to select from among the at least three unique multi-bit binary addresses based on the voltage level, the multi-bit binary address assuming a first value responsive to the voltage level being a first voltage level, a second value responsive to the voltage level being a second voltage level, and a third value responsive to the voltage level being a floating voltage level between the first voltage level and the second voltage level, the circuit component further configured to be connected to a clock signal line and a data signal line in an electronic device along with at least two other substantially identical circuit components also configured to be connected to the clock signal line and the data signal line, each of the circuit component and the at least two other substantially identical circuit components having a unique multi-bit binary address selected from among the at least three unique multi-bit binary addresses. ### Claim 2 (depends on 1) The circuit component of claim 1 wherein the floating voltage level is determined by a voltage divider circuit connected between a first terminal configured to receive the first voltage level and a second terminal configured to receive the second voltage level. ### Claim 3 (depends on 2) The circuit component of claim 2 wherein the voltage divider circuit is internal to the circuit component. ### Claim 4 (depends on 2) The circuit component of claim 2 wherein the voltage divider circuit is external to the circuit component. ### Claim 5 (depends on 2) The circuit component of claim 2 wherein the first voltage level corresponds to a supply voltage of the circuit component and the second voltage level corresponds to a ground reference voltage of the circuit component. ### Claim 6 (depends on 1) The circuit component of claim 1 further comprising electronic circuitry configured to determine the multi-bit binary address from the voltage level applied to the single electrical contact, the electronic circuitry including a voltage divider and a plurality of comparators, the single electrical contact in electrical contact with an input of each of the plurality of comparators. ### Claim 7 (depends on 1) The circuit component of claim 1 included in an RF electronic device module. ### Claim 8 (depends on 7) The circuit component of claim 7 included in an RF device. ### Claim 9 An electronic device comprising: a master circuit component; and a plurality of secondary circuit components, each of the plurality of secondary circuit components configured to be assigned a unique multi-bit binary address selected from among at least three unique multi-bit binary addresses by application of a voltage to a single electrical contact of each respective one of the plurality of secondary circuit components, different levels of the voltage applied to the single electrical contact being associated with different unique multi-bit binary addresses, the master circuit configured to define a particular one of the plurality of secondary circuit components to communicate with by transmitting one of the unique multi-bit binary addresses over a signal line electrically coupled to a communication interface in each of the plurality of secondary circuit components, wherein the master circuit component and the plurality of secondary circuit components communicate via a serial bus protocol including a clock signal line and a single data line, the electronic device being included in a radio frequency device. ### Claim 10 (depends on 9) The electronic device of claim 9 wherein each of the secondary circuit components is configured to select from among the at least three unique multi-bit binary addresses to assign to itself. ### Claim 11 (depends on 10) The electronic device of claim 10 wherein each of the secondary circuit components is configured to assign itself one of the at least three unique multi-bit binary addresses responsive to the single electrical contact not being coupled to one of a supply voltage of the electronic device and ground. ### Claim 12 (depends on 9) The electronic device of claim 9 wherein each of plurality of secondary circuit components is assigned one unique multi-bit binary address of the at least three unique multi-bit binary addresses responsive to a level of the voltage applied to the single electrical contact of each respective one of the plurality of secondary circuit components being between one pair of a plurality of pairs of voltage thresholds. ### Claim 13 (depends on 12) The electronic device of claim 12 wherein the plurality of pairs of voltage thresholds are defined by voltage divider circuits internal to each respective one of the plurality of secondary circuit components. ### Claim 14 (depends on 9) The electronic device of claim 9 wherein each of plurality of secondary circuit components is identical in design. ### Claim 15 A circuit component having a multi-bit binary address, the multi-bit binary address determined from a voltage level applied to a single electrical contact of the circuit component, the circuit component having electronic circuitry configured to determine the multi-bit binary address from the voltage level applied to the single electrical contact, the electronic circuitry including a voltage divider and a plurality of comparators, the single electrical contact in electrical contact with an input of each of the plurality of comparators, the circuit component configured to be assigned one of at least three unique multi-bit binary addresses and to select from among the at least three unique multi-bit binary addresses based on the voltage level, the circuit component further configured to be connected to a clock signal line and a data signal line in an electronic device along with at least two other substantially identical circuit components also configured to be connected to the clock signal line and the data signal line, each of the circuit component and the at least two other substantially identical circuit components having a unique multi-bit binary address selected from among the at least three unique multi-bit binary addresses.