Circuit arrangement with clock sharing, and corresponding method

A method comprising:

• receiving, by a slave circuit, an external clock signal from a master circuit;
• distributing to a plurality of peripheral circuits of the slave circuit a respective clock signal obtained from the external clock signal, wherein distributing the respective clock signal comprises sending the external clock signal according to at least two different timing modes for respective peripheral circuits of the plurality of peripheral circuits, wherein the plurality of peripheral circuits comprises a first peripheral circuit that uses the external clock signal in a first timing mode of the at least two different timing modes, and a second peripheral circuit that uses the external clock signal in a second timing mode of the at least two different timing modes;
• detecting a given operating mode of the slave circuit for accessing the second peripheral circuit;
• when the given operating mode is detected,
• requesting the external clock signal to operate according to the second timing mode by generating a locking signal and supplying the locking signal to the master circuit, and
• supplying the locking signal to the first peripheral circuit, wherein the second timing mode is different from the first timing mode;
• and
• following upon receipt of the locking signal, sending, by the master circuit, the external clock signal according to the second timing mode.

A circuit comprising:

• a clock terminal configured to receive a clock signal;
• a further terminal;
• a register bank;
• a first peripheral circuit having a clock input coupled to the clock terminal;
• a second peripheral circuit having a clock input coupled to the clock terminal;
• and
• a logic circuit, wherein the circuit is configured to operate in first and second modes, wherein, in the first mode, the first peripheral circuit is configured to access the register bank based on the clock signal having a first timing mode, and wherein, in the second mode:
• the logic circuit is configured to:
• activate a locking signal,
• provide the locking signal to the first peripheral circuit to prevent the first peripheral circuit from accessing the register bank, and
• provide the locking signal at the further terminal to request the clock signal to operate in a second timing mode different from the first timing mode, and
• the second peripheral circuit is configured to operate based on the clock signal having the second timing mode.