# US 11,115,009 B2 · Semiconductor integrated circuit

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- Number: US 11,115,009 B2
- Document ID: US11115009B2
- Status: Granted
- Kind: B2
- Application number: 16/928,229
- Filed: 2020-07-14
- Published: 2020-10-29
- Granted: 2021-09-07
- Earliest claimed: 2018-01-16
- Assignees: Nuvoton Technology Corporation Japan
- Applicants: Panasonic Semiconductor Solutions Co., Ltd.
- Inventors: Kazuyuki Nakanishi
- Web page: https://patentgrep.com/patent/US11115009B2

## CPC

- H03K 3/012: Modifications of generator to improve response time or to decrease power consumption
- H03K 3/3562: of the primary-secondary type
- G01R 31/28: Testing of electronic circuits, e.g. by signal tracer ({EMC, EMP or similar testing of electronic circuits G01R31/002;} testing for short-circuits, discontinuities, leakage or incorrect line connection G01R31/50; checking computers {or computer components} G06F11/00; checking static stores for correct operation G11C29/00 {; testing receivers or transmitters of transmission systems H04B17/00})
- G01R 31/318541: {Scan latches or cell details}
- H03K 3/037: Bistable circuits
- H03K 19/21: EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)

## Abstract

A semiconductor integrated circuit includes a first flip-flop that includes a first slave latch, a second flip-flop that includes a second slave latch, and a clock generation circuit that provides a common clock signal to the first flip-flop and the second flip-flop. The first slave latch includes a first inverter, a first feedback inverter that receives an output signal from the first inverter, and a first switch that is connected between an input terminal of the first inverter and an output terminal of the first feedback inverter. The first flip-flop outputs an output signal from the output terminal of the first feedback inverter.

## Claims

### Claim 1

A semiconductor integrated circuit, comprising:
a first flip-flop that includes a first input circuit, a first master latch that receives an output signal from the first input circuit, and a first slave latch that receives an output signal from the first master latch;
a second flip-flop that includes a second input circuit, a second master latch that receives an output signal from the second input circuit, and a second slave latch that receives an output signal from the second master latch; and
a clock generation circuit that provides a common clock signal to the first flip-flop and the second flip-flop, wherein
the first slave latch includes a first inverter, a first feedback inverter that receives an output signal from the first inverter, and a first switch that is connected between an input terminal of the first inverter and an output terminal of the first feedback inverter, and
the first flip-flop outputs a data output signal from the output terminal of the first feedback inverter to an outside of the semiconductor integrated circuit.

### Claim 2 (depends on 1)

The semiconductor integrated circuit according to claim 1, wherein
the first input circuit receives a first data input signal and a first scan input signal, and
the second input circuit receives a second data input signal and a signal outputted from the first inverter without a circuit between the second input circuit and the first inverter.

### Claim 3 (depends on 1)

The semiconductor integrated circuit according to claim 1, wherein
the first input circuit receives a first data input signal and a first scan input signal, and
the second input circuit receives a second data input signal and a signal to be inputted to the first inverter without a circuit between the second input circuit and the first inverter.

### Claim 4 (depends on 1)

The semiconductor integrated circuit according to claim 1, wherein
the first inverter is a 2-input NAND gate that receives a reset signal through one of input terminals.

### Claim 5 (depends on 1)

The semiconductor integrated circuit according to claim 1, wherein
the first feedback inverter is a 2-input NAND gate that receives a set signal through one of input terminals.