# US 11,115,007 B2 · Methods and apparatuses of a two-phase flip-flop with symmetrical rise and fall times > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,115,007 B2 - Document ID: US11115007B2 - Status: Granted - Kind: B2 - Application number: 16/294,640 - Filed: 2019-03-06 - Published: 2019-07-04 - Granted: 2021-09-07 - Earliest claimed: 2017-09-27 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Tyler J. Gomm; Yasuo Satoh - Web page: https://patentgrep.com/patent/US11115007B2 ## CPC - H03K 3/0372: {of the primary-secondary type} - H03K 3/017: Adjustment of width or dutycycle of pulses (pulse width modulation H03K7/08 {; to maintain energy constant H03K3/015}) - G11C 7/106: {Data output latches} - G11C 7/222: {Clock generating, synchronizing or distributing circuits within memory device} - G11C 11/4074: Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits - G11C 11/4076: Timing circuits (for regeneration management G11C11/406) - G11C 11/4085: {Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge} - G11C 11/4087: {Address decoders, e.g. bit - or word line decoders; Multiple line decoders} - G11C 11/4093: Input/output [I/O] data interface arrangements, e.g. data buffers - H03K 19/20: characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Methods and apparatuses of a two-phase flip-flop with symmetrical rise and fall times are disclosed herein. An example apparatus may include a clock generator circuit including a two-phase flip-flop circuit configured to provide an output signal. The two-phase flip-flop circuit includes a two-phase flip-flop and a driver circuit. The two-phase flip-flop is configured to provide a first driver control signal and a second driver control signal responsive to a clock signal. The first driver control signal and the second driver control signal are complementary. The driver circuit is configured to provide the output signal responsive to the first driver control signal and the second driver control signal. ## Claims ### Claim 1 An apparatus, comprising: a clock generator circuit comprising a two-phase flip-flop circuit configured to provide a first output signal and a second output signal, wherein the two-phase flip-flop circuit comprises a two-phase flip-flop coupled in series with a driver circuit, wherein the two-phase flip-flop is configured to provide, to the driver circuit, both a first driver control signal and a second driver control signal directly responsive to a same clock signal, wherein the first driver control signal and the second driver control signal are complementary, wherein first circuitry of the driver circuit is configured to provide the first output signal responsive to both of the first driver control signal and the second driver control signal, wherein second circuitry of the driver circuit is configured to provide the second output signal responsive to both of the first driver control signal and the second driver control signal, wherein the first output signal and the second output signal are complementary, wherein the first circuitry of the driver circuit comprises a pull-up passgate circuit configured to drive the first output signal to a logical high value responsive to the first and second control signals having first complementary values and a pull-down passgate circuit configured to drive the first output signal to a logical low value responsive to the first and second control signals having second complementary values, wherein the pull-up passgate circuit and the pull-down passgate circuit are each controlled by both of the first and second control signals. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the two-phase flip-flop comprises: a first circuit configured to receive a first signal and to propagate the first signal to a first output node in response to the same clock signal to provide the first driver control signal; and a second circuit configured to receive a complement of the first signal and to propagate the complement of the first signal to a second output node in response to the same clock signal to provide the second driver control signal. ### Claim 3 (depends on 2) The apparatus of claim 2, wherein a third circuit configured to receive an input signal and to provide the first signal at a third output node in response to the same clock signal and based on the input signal. ### Claim 4 (depends on 3) The apparatus of claim 3, wherein the third circuit comprises an inverter coupled to the third output node and configured to provide the complement of the first signal. ### Claim 5 (depends on 3) The apparatus of claim 3, wherein the third circuit comprises a clocked inverter configured to propagate the input signal to an output in response to the same clock signal, wherein the first signal is based on the output of the clocked inverter. ### Claim 6 (depends on 5) The apparatus of claim 5, wherein the third circuit further comprises a logic gate coupled between the clocked inverter and the third output node, wherein the logic gate is configured to provide the first signal to the output node based on an output of the clocked inverter and a reset signal. ### Claim 7 (depends on 2) The apparatus of claim 2, wherein the first circuit comprises a passgate configured to propagate the first signal to the first output node responsive to the same clock signal. ### Claim 8 (depends on 2) The apparatus of claim 2, wherein the second circuit comprises a passgate configured to propagate the complement of the first signal to the second output node responsive to the same clock signal. ### Claim 9 (depends on 1) The apparatus of claim 1, wherein the clock generator circuit further comprises a phase splitter configured to provide the same clock signal and a complementary clock signal responsive to an input clock signal. ### Claim 10 (depends on 1) The apparatus of claim 1, wherein the clock generator circuit further comprises: a first series of inverters configured to drive the first output signal to downstream circuitry; and a second series of inverters configured to drive the second output signal to the downstream circuitry, wherein a count of the first series of inverters is equal to a count of the second series of inverters. ### Claim 11 (depends on 1) The apparatus of claim 1, wherein the second circuitry of the driver circuit comprises a second pull-up circuit configured to drive the second output signal to the logical high value responsive to the first and second control signals and a second pull-down circuit configured to drive the second output signal to the logical low value responsive to the first and second control signals. ### Claim 12 (depends on 1) The apparatus of claim 1, wherein circuitry of the pull-up passgate circuit is schematically equivalent to circuitry of the pull-down passgate circuit. ### Claim 13 A method, comprising: receiving a clock signal at a clock generator circuit; providing, via a two-phase flip-flop of the clock generator circuit, both a first driver control signal and a second driver control signal directly responsive to the clock signal, wherein the first driver control signal and the second driver control signal are complementary; providing, via a first driver circuit of the clock generator circuit, a first output signal responsive to both of the first driver control signal and the second driver control signal, wherein providing the first output signal includes: driving, via a first passgate of the first driver circuit, the first output signal to a first logical value in response to the first and second control signals having first respective complementary values; and driving, via a second passgate of the first driver circuit, the first output signal to a second logical value in response to the first and second control signals having second respective complementary values, wherein the first passgate and the second passgate are each controlled by both of the first and second control signals; and providing, via a second driver circuit of the clock generator circuit that is coupled in parallel with the first driver circuit, a second output signal responsive to both of the first driver control signal and the second driver control signal, wherein the first output signal and the second output signal are complementary. ### Claim 14 (depends on 13) The method of claim 13, wherein circuitry of the first passgate is equivalent to circuitry of the second passgate. ### Claim 15 (depends on 13) The method of claim 13, further comprising causing the first driver control signal and the second driver control signal to transition to opposite logical values contemporaneously. ### Claim 16 A method comprising: receiving a clock signal at a clock generator circuit; providing, via a two-phase flip-flop of the clock generator circuit, both a first driver control signal and a second driver control signal directly responsive to the clock signal, wherein the first driver control signal and the second driver control signal are complementary; providing, via a first driver circuit of the clock generator circuit, a first output signal responsive to both of the first driver control signal and the second driver control signal, wherein providing the first output signal includes: driving, via a first passgate of the first driver circuit, the first output signal to a first logical value in response to the first and second control signals having first respective complementary values; and driving, via a second passgate of the first driver circuit, the first output signal to a second logical value in response to the first and second control signals having second respective complementary values providing, via a second driver circuit of the clock generator circuit that is coupled in parallel with the first driver circuit, a second output signal responsive to both of the first driver control, signal and the second driver control signal, wherein the first output signal and the second output signal are complementary, wherein providing the second output signal includes: driving, via a third passgate of the second driver circuit, the second output signal to the second logical value in response to the first and second control signals having the first respective complementary values; and driving, via a fourth passgate of the second driver circuit, the second output signal to the first logical value in response to the first and second control signals having the second respective complementary values.