Internal latch circuit and method for generating latch signal thereof

An internal latch circuit comprising:

• a first delay circuit receiving an input delay signal and an internal data strobe signal, and outputting a first internal input signal, wherein the input delay signal responds to a clock signal;
• a second delay circuit coupled to the first delay circuit, the second delay circuit receiving the internal data strobe signal, and outputting a first reverse internal input signal;
• a third delay circuit coupled to the second delay circuit, and receiving the internal data strobe signal and outputting a second internal input signal;
• a fourth delay circuit coupled to the third delay circuit, and receiving the internal data strobe signal and outputting a second reverse internal input signal;
• an internal latch signal generating circuit coupled to the first delay circuit, the second delay circuit, the third delay circuit, and the fourth delay circuit, and generating a first reverse pre-output signal according to the first internal input signal and the first reverse internal input signal, and generating a second reverse pre-output signal according to the second internal input signal and the second reverse internal input signal;
• and
• a NAND gate coupled to the internal latch signal generating circuit, and generating an internal latch signal according to the first reverse pre-output signal and the second reverse pre-output signal.