# US 11,114,850 B2 · Electrostatic discharge protection circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,114,850 B2 - Document ID: US11114850B2 - Status: Granted - Kind: B2 - Application number: 16/717,265 - Filed: 2019-12-17 - Published: 2020-06-25 - Granted: 2021-09-07 - Earliest claimed: 2018-12-21 - Assignees: Silicon Works Co., Ltd. - Applicants: Silicon Works Co., Ltd. - Inventors: Jae Min Kim; Jae Hyun Lee; Yong Nam Choi - Web page: https://patentgrep.com/patent/US11114850B2 ## CPC - H02H 9/046: {responsive to excess voltage appearing at terminals of integrated circuits} - H02H: EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS (indicating or signalling undesired working conditions G01R, e.g. G01R31/00, G08B; locating faults along lines G01R31/08; emergency protective devices H01H) ## Abstract An electrostatic discharge protection circuit includes a first internal circuit formed between a first power line and a first ground line, and configured to operate in a range between a first power and a first ground; a second internal circuit formed between a second power line and a second ground line, and configured to operate in a range between a second power having a level higher than the first power and a second ground; a signal line connecting an output terminal of the first internal circuit and an input terminal of the second internal circuit; and a protection circuit configured to form a bypass path for bypassing a stress due to electrostatic discharge when the electrostatic discharge occurs, between the signal line and the second ground line, to protect a semiconductor device of the second internal circuit from the electrostatic discharge. ## Claims ### Claim 1 An electrostatic discharge protection circuit comprising: a first internal circuit formed between a first power line and a first ground line, and configured to operate in a range between a first power and a first ground; a second internal circuit formed between a second power line and a second ground line, and configured to operate in a range between a second power having a level higher than the first power and a second ground; a signal line connecting an output terminal of the first internal circuit and an input terminal of the second internal circuit; and a protection circuit configured to form a bypass path for bypassing a stress due to electrostatic discharge by a semiconductor device which has the same breakdown voltage as the first internal circuit when the electrostatic discharge occurs, between the signal line and the second ground line, to protect a semiconductor device of the second internal circuit from the electrostatic discharge. ### Claim 2 (depends on 1) The electrostatic discharge protection circuit according to claim 1, wherein the protection circuit comprises: a first protection circuit configured to form a first bypass path that bypasses a stress due to electrostatic discharge, between the signal line and the second ground line when the electrostatic discharge occurs at the output terminal of the first internal circuit; and a second protection circuit configured to form a second bypass path that bypasses a stress due to electrostatic discharge, between the signal line and the second ground line when the electrostatic discharge occurs at the input terminal of the second internal circuit. ### Claim 3 (depends on 2) The electrostatic discharge protection circuit according to claim 2, wherein the first protection circuit is configured by the semiconductor device which has the same breakdown voltage as the first internal circuit. ### Claim 4 (depends on 2) The electrostatic discharge protection circuit according to claim 2, wherein the first protection circuit is configured using an NMOS (N-channel metal oxide semiconductor). ### Claim 5 (depends on 4) The electrostatic discharge protection circuit according to claim 4, wherein the NMOS has a gate which is connected to the second ground line and a body which is connected to the first ground line. ### Claim 6 (depends on 2) The electrostatic discharge protection circuit according to claim 2, wherein the second protection circuit is configured by a semiconductor device which has the same breakdown voltage as the second internal circuit. ### Claim 7 (depends on 6) The electrostatic discharge protection circuit according to claim 6, wherein the second protection circuit is configured using a diode, and the diode has an anode which is connected to the second ground line and a cathode which is connected to the signal line. ### Claim 8 (depends on 2) The electrostatic discharge protection circuit according to claim 2, wherein the first protection circuit is configured by an NMOS which has a breakdown voltage the same as the first internal circuit and lower than the second protection circuit, and wherein the second protection circuit is configured by a diode which has a breakdown voltage the same as the second internal circuit and higher than the first protection circuit. ### Claim 9 (depends on 1) The electrostatic discharge protection circuit according to claim 1, wherein the second internal circuit is a level shift circuit, and the protection circuit protects a semiconductor device which uses a thin gate oxide of the level shift circuit, from electrostatic discharge likely to occur in the signal line. ### Claim 10 (depends on 1) The electrostatic discharge protection circuit according to claim 1, further comprising: a back-to-back diode formed between the first ground line and the second ground line. ### Claim 11 An electrostatic discharge protection circuit comprising: an inverter formed between a first power line and a first ground line, and configured to operate in a range between a first power and a first ground; a level shift circuit formed between a second power line and a second ground line, and configured to operate in a range between a second power having a level higher than the first power and a second ground; a signal line connecting an output terminal of the inverter and an input terminal of the level shift circuit; a first protection circuit configured to form a first bypass path that bypasses a stress due to electrostatic discharge by a semiconductor device which has the same breakdown voltage as the inverter, between the signal line and the second ground line when the electrostatic discharge occurs at the output terminal of the inverter, to protect a semiconductor device of the level shift circuit; and a second protection circuit configured to form a second bypass path that bypasses a stress due to electrostatic discharge, between the signal line and the second ground line when the electrostatic discharge occurs at the input terminal of the level shift circuit, to protect the semiconductor device of the level shift circuit. ### Claim 12 (depends on 11) The electrostatic discharge protection circuit according to claim 11, wherein the first protection circuit is configured by an NMOS which has the same breakdown voltage as the semiconductor device of the inverter. ### Claim 13 (depends on 11) The electrostatic discharge protection circuit according to claim 11, wherein the NMOS has a gate which is connected to the second ground line and a body which is connected to the first ground line. ### Claim 14 (depends on 11) The electrostatic discharge protection circuit according to claim 11, wherein the second protection circuit is configured by a diode which has the same breakdown voltage as the semiconductor device of the level shift circuit. ### Claim 15 (depends on 14) The electrostatic discharge protection circuit according to claim 14, wherein the diode has an anode which is connected to the second ground line and a cathode which is connected to the signal line. ### Claim 16 (depends on 11) The electrostatic discharge protection circuit according to claim 11, further comprising: a back-to-back diode formed between the first ground line and the second ground line. ### Claim 17 (depends on 11) The electrostatic discharge protection circuit according to claim 11, wherein the first and second protection circuits protect a semiconductor device which uses a thin gate oxide of the level shift circuit, from electrostatic discharge. ### Claim 18 An electrostatic discharge protection circuit comprising: first and second internal circuits configured to be driven in different voltage ranges; and first and second protection circuits configured to form first and second bypass paths for bypassing a stress due to electrostatic discharge by a semiconductor device which has the same breakdown voltage as a semiconductor device of an internal circuit driven in a lower voltage range between the first and second internal circuits, when the electrostatic discharge occurs between the first and second internal circuits, to protect semiconductor devices of the first and second internal circuits. ### Claim 19 (depends on 18) The electrostatic discharge protection circuit according to claim 18, wherein the first protection circuit is configured by an NMOS which has the same breakdown voltage as the semiconductor device of the internal circuit driven in the lower voltage range between the first and second internal circuits, the NMOS having a gate which is connected to a ground line of a high voltage and a body which is connected to a ground line of a low voltage. ### Claim 20 (depends on 19) The electrostatic discharge protection circuit according to claim 19, wherein the second protection circuit is configured by a diode which has the same breakdown voltage as the semiconductor device of the internal circuit driven in a higher voltage range between the first and second internal circuits, the diode having an anode which is connected to a ground line of a high voltage and a cathode which is connected to a signal line interconnecting input and output signals of the first and second internal circuits.