# US 11,114,847 B1 · High speed data transient protection > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,114,847 B1 - Document ID: US11114847B1 - Status: Granted - Kind: B1 - Application number: 15/920,125 - Filed: 2018-03-13 - Granted: 2021-09-07 - Earliest claimed: 2018-03-13 - Assignees: Rockwell Collins, Inc. - Applicants: Rockwell Collins, Inc. - Inventors: Lawrence M. Blumer - Web page: https://patentgrep.com/patent/US11114847B1 ## CPC - H02H 9/045: {adapted to a particular application and not provided for elsewhere} - H04B 3/04: Control of transmission; Equalising - H02H: EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS (indicating or signalling undesired working conditions G01R, e.g. G01R31/00, G08B; locating faults along lines G01R31/08; emergency protective devices H01H) - H04B: TRANSMISSION ## Abstract A high bandwidth data interface in an aircraft includes a pulse tolerant, non-inductive resistor for reducing surge current due to lightning transients, and a very low capacitance transient voltage suppressor to suppress the lightning transient voltages. A cable equalizer/redriver then recovers the original high bandwidth input signal. The high bandwidth interface is thereby able to survive DO-160 section 22 level 3 and 4 lightning transients. ## Claims ### Claim 1 A transient voltage suppression circuit comprising: an ultra-low capacitance transient voltage suppressor; and a cable equalizer in electronic communication with the transient voltage suppressor, wherein: the transient voltage suppressor is configured to remove lightning transients from a signal having at least one gigahertz bandwidth; and the cable equalizer is configured to boost a filtered signal from the transient voltage suppressor. ### Claim 2 (depends on 1) The circuit of claim 1, further comprising a resistor in electronic communication with the transient voltage suppressor. ### Claim 3 (depends on 2) The circuit of claim 2, wherein the resistor comprises a pulse tolerant non-inductive resistor of between 70 and 80 ohms. ### Claim 4 (depends on 1) The circuit of claim 1, wherein the transient voltage suppressor is connected to the cable equalizer via a capacitor interposed between the transient voltage suppressor and a serial data input of the cable equalizer. ### Claim 5 (depends on 1) The circuit of claim 1, wherein the cable equalizer comprises a pair of parallel capacitors connected to a complimentary serial data input of the cable equalizer. ### Claim 6 (depends on 1) The circuit of claim 1, wherein the cable equalizer comprises a serial data output and a complimentary serial data output, each of the serial data output and complimentary serial data output connected to a corresponding output capacitor, and an output resistor interposed between the serial data output and complimentary serial data output. ### Claim 7 A computer system including a transient voltage suppression circuit comprising: a resistor; a transient voltage suppressor in electronic communication with the resistor; and a cable equalizer in electronic communication with the transient voltage suppressor via a capacitor interposed between the transient voltage suppressor and a serial data input of the cable equalizer, wherein: the transient voltage suppressor is configured to remove lightning transients from a signal having at least one gigahertz bandwidth; and the cable equalizer is configured to boost a filtered signal from the transient voltage suppressor. ### Claim 8 (depends on 7) The computer system of claim 7, wherein the resistor comprises a pulse tolerant non-inductive resistor of between 70 and 80 ohms. ### Claim 9 (depends on 7) The computer system of claim 7, wherein the transient voltage suppressor comprises an ultra-low capacitance transient voltage suppressor. ### Claim 10 (depends on 7) The computer system of claim 7, wherein the cable equalizer comprises a pair of parallel capacitors connected to a complimentary serial data input of the cable equalizer, a first capacitor in the pair of parallel capacitors comprising an approximately 1 μF capacitor and a second capacitor in the pair of parallel capacitors comprising a 0.001 μF capacitor. ### Claim 11 (depends on 7) The computer system of claim 7, wherein the cable equalizer comprises a serial data output and a complimentary serial data output, each of the serial data output and complimentary serial data output connected to a corresponding output capacitor of between 4 μF and 5 μF, and an output resistor of between 90 and 110 ohms interposed between the serial data output and complimentary serial data output. ### Claim 12 An aircraft comprising: a transient voltage suppression circuit comprising: a transient voltage suppressor; a pulse tolerant non-inductive resistor of between 70 and 80 ohms in electronic communication with the transient voltage suppressor; and a cable equalizer in electronic communication with the transient voltage suppressor, wherein: the transient voltage suppressor is configured to remove lightning transients from a signal having at least one gigahertz bandwidth; and the cable equalizer is configured to boost a filtered signal from the transient voltage suppressor. ### Claim 13 (depends on 12) The aircraft of claim 12, wherein the transient voltage suppressor comprises an ultra-low capacitance transient voltage suppressor. ### Claim 14 (depends on 12) The aircraft of claim 12, wherein the transient voltage suppressor is connected to the cable equalizer via a capacitor interposed between the transient voltage suppressor and a serial data input of the cable equalizer. ### Claim 15 (depends on 12) The aircraft of claim 12, wherein the cable equalizer comprises a pair of parallel capacitors connected to a complimentary serial data input of the cable equalizer. ### Claim 16 (depends on 12) The aircraft of claim 12, wherein the cable equalizer comprises a serial data output and a complimentary serial data output, each of the serial data output and complimentary serial data output connected to a corresponding output capacitor, and an output resistor interposed between the serial data output and complimentary serial data output.