Photonic chip passed through by a via

A photonic chip, lying in a plane, the photonic chip comprising:

• a substrate having an upper face and a lower face that are parallel to the plane of the chip, this substrate comprising, between the upper and lower faces:
• an interconnection layer of thickness larger than 50 μm, this interconnection layer being devoid of optical components, an optical layer bonded, at a bonding interface, to the interconnection layer, at least one optical component buried in an interior of the optical layer, an electrical terminal chosen from a group consisting of an electrical contact embedded in the interior of the optical layer, this embedded electrical contact being that of the optical component or of an electronic component, and of an electrical track produced on the upper face of the substrate, electrical connection pads produced on the lower face of the substrate, each of these pads being able to be electrically connected by way of a solder bump to another carrier, a primary via extending through the interconnection layer from the lower face in order to electrically connect one of the connection pads to the electrical terminal, this primary via having a diameter larger than or equal to 10 μm, wherein:
• the thickness of the optical layer is smaller than 15 μm, the primary via extends through the interconnection layer solely between the lower face and the bonding interface so that the primary via does not extend into the interior of the optical layer, the photonic chip comprises a secondary via that extends the primary via into the interior of the optical layer in order to electrically connect the primary via to the electrical terminal, this secondary via extending in the interior of the optical layer from the bonding interface to the electrical terminal, a maximum diameter of the secondary via being smaller than 3 μm, and the electrical terminal is the embedded electrical contact of the optical component or of the electronic component, the photonic chip comprises:
• an electrical track produced on the upper face of the substrate, a metal line embedded in the interior of the optical layer, this metal line being electrically connected to the electrical terminal and mainly extending parallel to the plane of the chip, a tertiary via that extends from the embedded metal line to the electrical track produced on the upper face of the substrate, the diameter of this tertiary via being smaller than 3 μm.

A photonic chip lying in a plane, the photonic chip comprising:

• a substrate having an upper face and a lower face that are parallel to the plane of the chip, this substrate comprising, between the upper and lower faces:
• an interconnection layer of thickness larger than 50 μm, this interconnection layer being devoid of optical components,
• an optical layer bonded, at a bonding interface, to the interconnection layer,
• at least one optical component buried in an interior of the optical laver,
• an electrical terminal chosen from a group consisting of an electrical contact embedded in the interior of the optical layer, this embedded electrical contact being that of the optical component or of an electronic component, and of an electrical track produced on the upper face of the substrate,
• electrical connection pads produced on the lower face of the substrate, each of these pads being able to be electrically connected by way of a solder bump to another carrier,
• a primary via extending through the interconnection layer from the lower face in order to electrically connect one of the connection pads to the electrical terminal, this primary via having a diameter larger than or equal to 10 μm, wherein:
• the thickness of the optical layer is smaller than 15 μm,
• the primary via extends through the interconnection layer solely between the lower face and the bonding interface so that the primary via does not extend into the interior of the optical layer,
• the photonic chip comprises a secondary via that extends the primary via into the interior of the optical layer in order to electrically connect the primary via to the electrical terminal, this secondary via extending in the interior of the optical layer from the bonding interface to the electrical terminal, a maximum diameter of the secondary via being smaller than 3 μm,
• the optical layer comprises successively, from the upper face to the bonding interface:
• an oxide sublayer, at least one portion of the optical component or of the electronic component being produced on the side of this oxide sublayer that is turned toward the bonding interface, and
• an encapsulation sublayer in which said at least one portion of the optical or electronic component is encapsulated in a dielectric material,
• said at least one portion of the optical component or of the electronic component comprises an electrical contact embedded in the interior of the encapsulation sublayer,
• the optical chip comprises an additional via that extends in the interior of the optical layer from the bonding interface to the embedded electrical contact of said at least one portion of the optical component or of the electronic component, this additional via being made from a material the thermal conductivity of which is higher than 1.2*C122, where C122 is the thermal conductivity of the dielectric material of the encapsulation sublayer.