# US 11,114,736 B2 · Multi-channel power combiner with phase adjustment > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,114,736 B2 - Document ID: US11114736B2 - Status: Granted - Kind: B2 - Application number: 16/835,303 - Filed: 2020-03-31 - Published: 2020-10-01 - Granted: 2021-09-07 - Earliest claimed: 2019-03-27 - Assignees: Globalfoundries Inc. - Applicants: Globalfoundries Inc. - Inventors: See Taur Lee; Sher Jiung Fang; Abdellatif Bellaouar - Web page: https://patentgrep.com/patent/US11114736B2 ## CPC - H01P 5/12: Coupling devices having more than two ports (H01P5/04 takes precedence) - H03F 3/245: {with semiconductor devices only} - H03K 5/01: Shaping pulses (discrimination against noise or interference H03K5/125) - H03K 17/687: the devices being field-effect transistors - H03K 17/6872: {using complementary field-effect transistors} - H01P 11/00: Apparatus or processes specially adapted for manufacturing waveguides or resonators, lines, or other devices of the waveguide type - H03F 2200/451: the amplifier being a radio frequency amplifier - H03K 2005/00286: {Phase shifter, i.e. the delay between the output and input pulse is dependent on the frequency, and such that a phase difference is obtained independent of the frequency} - H03K 2217/0018: Special modifications or use of the back gate voltage of a FET - H01P: WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE (operating at optical frequencies G02B) - H03F: AMPLIFIERS - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract Power combiners having increased output power, such as may be useful in millimeter-wave devices. The power combiner comprise at least two channels, wherein each channel comprises a phase alignment circuit, wherein the phase alignment circuit comprises a first differential input subcircuit comprising a first inverter and a second inverter, and a second differential input subcircuit comprising a third inverter and a fourth inverter, wherein the first inverter, the second inverter, the third inverter, and the fourth inverter each comprise a PMOS transistor and an NMOS transistor each having an adjustable back gate bias voltage. By adjusting the back gate bias voltage, the phases of the signal through each channel may be aligned, which may increase the output power of the power combiner. Methods of increasing output power of such power combiners. Systems for manufacturing devices comprising such power combiners. ## Claims ### Claim 1 A semiconductor device, comprising: a multi-channel power combiner, comprising: at least two channels, wherein each channel comprises: a phase alignment circuit comprising a plurality of PMOS transistors and NMOS transistors each having an adjustable back gate bias voltage; at least one frequency multiplier after the phase alignment circuit; and at least one power amplifier after the at least one frequency multiplier and configured to amplify the power of a differential output of the phase alignment circuit; at least one back gate voltage generator configured to provide the adjustable back gate bias voltage to at least one of the transistors; a power combiner circuit configured to combine the power of the outputs of each channel, to yield a combined output having a power; a sensor configured to sense the power of the combined output; and a control circuit configured to adjust the back gate bias voltage provided by the at least one back gate voltage generator, based at least in part on the power of the combined output sensed by the sensor, wherein the back gate bias voltage may be used to adjust the phase of the input signal received by the phase alignment circuit. ### Claim 2 (depends on 1) The semiconductor device of claim 1, wherein: the phase alignment circuit comprises a first differential input subcircuit comprising a first inverter and a second inverter, and a second differential input subcircuit comprising a third inverter and a fourth inverter, wherein the first inverter, the second inverter, the third inverter, and the fourth inverter each comprises at least one of the PMOS transistors and at least one of the NMOS transistors; and each of the first differential input subcircuit and the second differential input subcircuit further comprises an AC-coupled capacitor and a feedback resistor. ### Claim 3 (depends on 2) The semiconductor device of claim 2, wherein the phase alignment circuit further comprises a pair of cross-coupled inverters in parallel to the second inverter and the fourth inverter. ### Claim 4 (depends on 1) The semiconductor device of claim 1, wherein each channel further comprises an output subcircuit comprising an AC-coupled capacitor and a resistor. ### Claim 5 (depends on 1) The semiconductor device of claim 1, wherein each channel further comprises an injection-locked power amplifier (ILPA) after the at least one frequency multiplier and before the power amplifier. ### Claim 6 (depends on 1) The semiconductor device of claim 1, wherein the at least one frequency multiplier of each channel comprises two push-pull frequency doublers (PPFDs) in series configured to receive output from the phase alignment circuit. ### Claim 7 (depends on 1) The semiconductor device of claim 1, wherein the PMOS and the NMOS transistors are formed using a fully-depleted silicon-on-insulator (FDSOI) process. ### Claim 8 A system, comprising: a semiconductor device processing system to manufacture a semiconductor device; and a processing controller operatively coupled to said semiconductor device processing system, said processing controller configured to control an operation of the semiconductor device processing system; wherein the semiconductor device processing system is adapted to: form a multi-channel power combiner, comprising: at least two channels, wherein each channel comprises: a phase alignment circuit comprising a plurality of PMOS transistors and NMOS transistors each having an adjustable back gate bias voltage; at least one frequency multiplier after the phase alignment circuit; and at least one power amplifier after the at least one frequency multiplier and configured to amplify the power of a differential output of the phase alignment circuit; form at least one back gate voltage generator configured to provide the adjustable back gate bias voltage to at least one of the transistors; form a power combiner circuit configured to combine the power of the outputs of each channel, to yield a combined output having a power; form a sensor configured to sense the power of the combined output; and form a control circuit configured to adjust the back gate bias voltage provided by the at least one back gate voltage generator, based at least in part on the power of the combined output sensed by the sensor. ### Claim 9 (depends on 8) The system of claim 8, wherein: the phase alignment circuit comprises a first differential input subcircuit comprising a first inverter and a second inverter, and a second differential input subcircuit comprising a third inverter and a fourth inverter, wherein the first inverter, the second inverter, the third inverter, and the fourth inverter each comprises at least one of the PMOS transistors and at least one of the NMOS transistors; and the semiconductor device processing system is adapted to form each of the first differential input subcircuit and the second differential input subcircuit to further comprise an AC-coupled capacitor and a feedback resistor. ### Claim 10 (depends on 9) The system of claim 9, wherein the semiconductor device processing system is adapted to form the phase alignment circuit to further comprise a pair of cross-coupled inverters in parallel to the second inverter and the fourth inverter. ### Claim 11 (depends on 8) The system of claim 8, wherein the semiconductor device processing system is adapted to form an output subcircuit of each channel, wherein the output subcircuit comprises an AC-coupled capacitor and a resistor. ### Claim 12 (depends on 8) The system of claim 8, wherein the semiconductor device processing system is adapted to form each channel to further comprise an injection-locked power amplifier (ILPA) after the at least one frequency multiplier. ### Claim 13 (depends on 8) The system of claim 8, wherein the semiconductor device processing system is adapted to form the at least one frequency multiplier of each channel by forming two push-pull frequency doublers (PPFDs) in series configured to receive output from the phase alignment circuit. ### Claim 14 A semiconductor device, comprising: a multi-channel power combiner, comprising: at least two channels, wherein each channel comprises: a phase alignment circuit comprising a plurality of PMOS transistors and NMOS transistors each having an adjustable back gate bias voltage, and an injection-locked power amplifier (ILPA) after the phase alignment circuit; at least one back gate voltage generator configured to provide the adjustable back gate bias voltage to at least one of the transistors; a power combiner circuit configured to combine the power of the outputs of each channel, to yield a combined output having a power; a sensor configured to sense the power of the combined output; and a control circuit configured to adjust the back gate bias voltage provided by the at least one back gate voltage generator, based at least in part on the power of the combined output sensed by the sensor, wherein the back gate bias voltage may be used to adjust the phase of the input signal received by the phase alignment circuit. ### Claim 15 (depends on 14) The semiconductor device of claim 14, further comprising: at least one power amplifier after the ILPA and configured to amplify the power of a differential output of the phase alignment circuit. ### Claim 16 (depends on 14) The semiconductor device of claim 14, wherein each channel further comprises at least one frequency multiplier. ### Claim 17 (depends on 16) The semiconductor device of claim 16, wherein the at least one frequency multiplier of each channel comprises two push-pull frequency doublers (PPFDs) in series configured to receive output from the phase alignment circuit.