# US 11,114,613 B2 · Cross-point memory and methods for forming of the same

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 11,114,613 B2
- Document ID: US11114613B2
- Status: Granted
- Kind: B2
- Application number: 16/866,302
- Filed: 2020-05-04
- Published: 2020-08-20
- Granted: 2021-09-07
- Earliest claimed: 2014-08-25
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Fabio Pellizzer; Innocenzo Tortorelli; Andrea Ghetti
- Web page: https://patentgrep.com/patent/US11114613B2

## CPC

- H10N 70/231: {based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect}
- H10B 63/24: {of the Ovonic threshold switching type}
- H10B 63/80: {Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays}
- H10B 63/845: {the switching components being connected to a common vertical conductor}
- H10N 70/063: {by etching of pre-deposited switching material layers, e.g. lithography}
- H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices}
- H10N 70/8828: {Tellurides, e.g. GeSbTe}
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

The disclosed technology generally relates to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. Line stacks are formed, including a storage material line disposed over lower a conductive line. Upper conductive lines are formed over and crossing the line stacks, exposing portions of the line stacks between adjacent upper conductive lines. After forming the upper conductive lines, storage elements are formed at intersections between the lower conductive lines and the upper conductive lines by removing storage materials from exposed portions of the line stacks, such that each storage element is laterally surrounded by spaces. A continuous sealing material laterally surrounds each of the storage elements.

## Claims

### Claim 1

A memory device, comprising:
a plurality of first conductive lines;
a plurality of memory cell pillars disposed over the plurality of first conductive lines, wherein each of the memory cell pillars comprises a selector material element and a storage material element disposed above the selector material element;
a first isolation material positioned between the plurality of first conductive lines and between the selector material elements of the plurality of memory cell pillars; and
a sealing material laterally surrounding each storage material element and disposed between a topmost surface of the first isolation material and at least one conductive line of a plurality of second conductive lines different than the plurality of first conductive lines.

### Claim 2 (depends on 1)

The memory device of claim 1, further comprising:
a second isolation material surrounding the sealing material.

### Claim 3 (depends on 1)

The memory device of claim 1, wherein the sealing material contacts at least two sidewalls of each selector material element.

### Claim 4 (depends on 1)

The memory device of claim 1,
wherein the plurality of first conductive lines extends in a first direction and the plurality of second conductive lines extends in a second direction crossing the first direction.

### Claim 5 (depends on 4)

The memory device of claim 4, wherein the sealing material
contacts the first isolation material and extends to contact one of the plurality of second conductive lines.

### Claim 6 (depends on 1)

The memory device of claim 1, wherein the sealing material contacts at least two sidewalls of each storage material element.

### Claim 7 (depends on 1)

The memory device of claim 1, further comprising:
a second sealing material contacting a first and second sidewall of each selector material element and storage material element of the plurality of memory cell pillars.

### Claim 8 (depends on 1)

The memory device of claim 1, further comprising:
a second isolation material positioned between the sealing material and the plurality of memory cell pillars and disposed above the first isolation material.

### Claim 9

A method, comprising:
forming a plurality of line stacks, wherein each of the plurality of line stacks includes an active material line disposed over one of a plurality of lower conductive lines;
filling, after forming the plurality of line stacks, an isolation material in gaps between the plurality of line stacks;
forming, after filling the gaps, a plurality of active elements at intersections between the plurality of lower conductive lines and a plurality of upper conductive lines by removing active material from the active material line; and
forming a plurality of memory storage elements, wherein each of the plurality of memory storage elements is vertically interposed above one of the plurality of active elements and below one of the plurality of upper conductive lines.

### Claim 10 (depends on 9)

The method of claim 9, wherein a first sidewall and a second sidewall of each of the plurality of active elements is exposed based at least in part on removing active material from the active material line, and wherein a third sidewall and a fourth sidewall of each of the plurality of active elements is surrounded by the isolation material based at least in part on filing the gaps between the plurality of line stacks.

### Claim 11 (depends on 9)

The method of claim 9, further comprising:
forming a sealing material contacting a first sidewall and a second sidewall of each of the plurality of active elements.

### Claim 12 (depends on 11)

The method of claim 11, wherein forming the sealing material further comprises:
forming the sealing material laterally surrounding each of the plurality of memory storage elements.

### Claim 13 (depends on 9)

The method of claim 9, wherein forming the plurality of memory storage elements comprises:
forming the plurality of memory storage elements by removing memory storage material from a memory storage material line in each of the plurality of line stacks such that each of the plurality of memory storage elements is laterally surrounded by spaces.

### Claim 14 (depends on 13)

The method of claim 13, further comprising:
removing an upper portion of the isolation material to expose sidewalls of the memory storage material lines and expose sidewalls of an electrode disposed below the memory storage material lines.

### Claim 15 (depends on 9)

The method of claim 9, wherein the plurality of active elements are selector elements.