# US 11,114,612 B2 · Magnetoresistive random access memory and method for fabricating the same

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- Number: US 11,114,612 B2
- Document ID: US11114612B2
- Status: Granted
- Kind: B2
- Application number: 16/708,389
- Filed: 2019-12-09
- Published: 2021-05-13
- Granted: 2021-09-07
- Earliest claimed: 2019-11-11
- Assignees: United Microelectronics Corp.
- Applicants: United Microelectronics Corp.
- Inventors: Da-Jun Lin; Bin-Siang Tsai; Shih-Wei Su; Ting-An Chien
- Web page: https://patentgrep.com/patent/US11114612B2

## CPC

- H10N 50/01: Manufacture or treatment
- G11C 11/161: {details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell}
- H01F 10/3254: {the spacer being semiconducting or insulating, e.g. for spin tunnel junction [STJ]}
- H01F 41/308: {lift-off processes, e.g. ion milling, for trimming or patterning}
- H01F 41/34: in patterns, e.g. by lithography
- H10B 61/00: Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
- H10N 50/10: Magnetoresistive devices
- H10N 50/80: Constructional details
- H10N 50/85: Materials of the active region
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H01F: MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A method for fabricating semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) stack on a substrate, in which the MTJ stack includes a pinned layer on the substrate, a barrier layer on the pinned layer, and a free layer on the barrier layer. Next, part of the MTJ stack is removed, a first cap layer is formed on a sidewall of the MTJ stack, and the first cap layer and the MTJ stack are removed to form a first MTJ and a second MTJ.

## Claims

### Claim 1

A method for fabricating semiconductor device, comprising:
forming a magnetic tunneling junction (MTJ) stack on a substrate;
removing part of the MTJ stack;
forming a first cap layer on a sidewall of the MTJ stack; and
removing portions of the first cap layer and portions of the MTJ stack to form a first MTJ and a second MTJ.

### Claim 2 (depends on 1)

The method of claim 1, wherein the MTJ stack comprises a pinned layer on the substrate, a barrier layer on the pinned layer, and a free layer on the barrier layer, the method comprising:
forming a top electrode on the MTJ stack;
removing the top electrode and the free layer;
forming the first cap layer on sidewalls of the top electrode and the free layer; and
removing the first cap layer, the barrier layer, and the pinned layer to form the first MTJ and the second MTJ.

### Claim 3 (depends on 2)

The method of claim 2, wherein the free layer comprises:
a first free layer on the barrier layer;
a stop layer on the first free layer; and
a second free layer on the stop layer.

### Claim 4 (depends on 3)

The method of claim 3, further comprising:
forming a hard mask on the top electrode;
removing the hard mask, the top electrode and the second free layer; and
forming the first cap layer on sidewalls of the top electrode, the second free layer, the stop layer, and the first free layer and a top surface of the barrier layer.

### Claim 5 (depends on 4)

The method of claim 4, further comprising:
forming a second cap layer on the hard mask and the first cap layer; and
removing the second cap layer, the first cap layer, the hard mask, the barrier layer, and the pinned layer to form a first spacer and a second spacer adjacent to the free layer and the top electrode.

### Claim 6 (depends on 5)

The method of claim 5, wherein a sidewall of the first spacer is aligned with a sidewall of the barrier layer.

### Claim 7 (depends on 5)

The method of claim 5, wherein a sidewall of the second spacer is aligned with a sidewall of the barrier layer.

### Claim 8 (depends on 5)

The method of claim 5, further comprising:
performing an oxidation process to form a third spacer on sidewalls of the barrier layer and the pinned layer; and
forming a third cap layer on the top electrode, the second spacer, and the third spacer.

### Claim 9 (depends on 8)

The method of claim 8, further comprising performing the oxidation process to form a fourth spacer on the third spacer.

### Claim 10 (depends on 8)

The method of claim 8, wherein the third cap layer comprises a hydrogen-free dielectric layer.

### Claim 11 (depends on 1)

The method of claim 1, further comprising performing an oxidation process to form the first cap layer.

### Claim 12

A semiconductor device, comprising:
a magnetic tunneling junction (MTJ) on a substrate, wherein the MTJ comprises:
a pinned layer on the substrate;
a barrier layer on the pinned layer; and
a free layer on the barrier layer, wherein a critical dimension of a bottom surface of the free layer is different from a critical dimension of a top surface of the barrier layer.

### Claim 13 (depends on 12)

The semiconductor device of claim 12, wherein a width of the free layer is less than a width of the pinned layer.

### Claim 14 (depends on 12)

The semiconductor device of claim 12, further comprising a reference layer between the barrier and the pinned layer.

### Claim 15 (depends on 14)

The semiconductor device of claim 14, wherein a width of the free layer is less than a width of the reference layer.

### Claim 16 (depends on 14)

The semiconductor device of claim 14, wherein the free layer and the reference layer comprise same material.

### Claim 17 (depends on 14)

The semiconductor device of claim 14, further comprising:
a first spacer on sidewalls of the free layer;
a second spacer on the first spacer; and
a third spacer on sidewalls of the reference layer and pinned layer.

### Claim 18 (depends on 17)

The semiconductor device of claim 17, wherein the first spacer comprises a L-shape.

### Claim 19 (depends on 17)

The semiconductor device of claim 17, further comprising a cap layer on sidewalls of the third spacer.

### Claim 20 (depends on 19)

The semiconductor device of claim 19, wherein the cap layer comprises a hydrogen-free dielectric layer.