# US 11,114,610 B2 · Semiconductor structure, electrode structure and method of forming the same

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 11,114,610 B2
- Document ID: US11114610B2
- Status: Granted
- Kind: B2
- Application number: 16/668,775
- Filed: 2019-10-30
- Published: 2020-02-27
- Granted: 2021-09-07
- Earliest claimed: 2016-01-15
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company Ltd.
- Inventors: Chung-Yen Chou; Fu-Ting Sung; Yao-Wen Chang; Shih-Chang Liu
- Web page: https://patentgrep.com/patent/US11114610B2

## CPC

- H10N 50/10: Magnetoresistive devices
- H10N 50/01: Manufacture or treatment
- H10N 50/80: Constructional details
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

## Abstract

A semiconductor structure includes an Nth metal layer, a diffusion barrier layer over the Nth metal layer, a first deposition of bottom electrode material over the diffusion barrier layer, a second deposition of bottom electrode material over the first deposition of bottom electrode material, a magnetic tunneling junction (MTJ) layer over the second deposition of bottom electrode material, a top electrode over the MTJ layer; and an (N+1)th metal layer over the top electrode; wherein the diffusion barrier layer and the first deposition of bottom electrode material are laterally in contact with a dielectric layer, the first deposition of bottom electrode material spacing the diffusion barrier layer and the second deposition of bottom electrode material apart, and N is an integer greater than or equal to 1. An associated electrode structure and method are also disclosed.

## Claims

### Claim 1

A semiconductor structure, comprising:
a diffusion barrier layer;
a first deposition of electrode material over the diffusion barrier layer;
a second deposition of electrode material over the first deposition of electrode material;
a magnetic tunneling junction (MTJ) layer over the second deposition of electrode material; and
a top electrode over the MTJ layer;
wherein the diffusion barrier layer and the first deposition of electrode material are laterally in contact with a dielectric layer, the first deposition of electrode material spacing the diffusion barrier layer and the second deposition of electrode material apart, and the diffusion barrier layer protrudes a center region thereof from a top surface of the diffusion barrier layer toward the MTJ layer.

### Claim 2 (depends on 1)

The semiconductor structure of claim 1, wherein the first deposition of electrode material and a portion of the diffusion barrier layer form a tapered structure.

### Claim 3 (depends on 1)

The semiconductor structure of claim 1, wherein the diffusion barrier layer includes metal nitride materials.

### Claim 4 (depends on 1)

The semiconductor structure of claim 1, wherein a sidewall of the MTJ is surrounded by a protection layer.

### Claim 5 (depends on 4)

The semiconductor structure of claim 4, wherein a sidewall of the second deposition of electrode material is surrounded by the protection layer.

### Claim 6 (depends on 5)

The semiconductor structure of claim 5, wherein a sidewall of the top electrode is surrounded by the protection layer.

### Claim 7 (depends on 1)

The semiconductor structure of claim 1, wherein the dielectric layer includes silicon carbide (SiC) or silicon-rich oxide (SRO).

### Claim 8 (depends on 1)

The semiconductor structure of claim 1, wherein the first deposition of electrode material and the second deposition of electrode material include TiN.

### Claim 9 (depends on 1)

The semiconductor structure of claim 1, wherein the semiconductor structure is a magnetic random access memory (MRAM) cell.

### Claim 10

A semiconductor structure, comprising:
a dielectric layer;
a diffusion barrier layer disposed in the dielectric layer;
a bottom electrode over the diffusion barrier layer;
a magnetic tunneling junction (MTJ) layer over the bottom electrode; and
a top electrode over the MTJ layer;
wherein a top surface of the diffusion barrier layer is lower than a top surface of the dielectric layer, and a bottom surface of the bottom electrode in contact with the diffusion barrier layer is uneven, and a center region of the bottom surface of the bottom electrode is higher than an outer region of the bottom surface of the bottom electrode, and a top surface of the bottom electrode in contact with the MTJ layer is even.

### Claim 11 (depends on 10)

The semiconductor structure of claim 10, wherein the dielectric layer includes a silicon carbide (SiC) layer.

### Claim 12 (depends on 11)

The semiconductor structure of claim 11, wherein the dielectric layer further includes a silicon-rich oxide (SRO) layer over the SiC layer.

### Claim 13 (depends on 10)

The semiconductor structure of claim 10, wherein the bottom electrode includes titanium nitride (TiN).

### Claim 14 (depends on 10)

The semiconductor structure of claim 10, wherein the diffusion barrier layer includes metal nitride materials.

### Claim 15 (depends on 14)

The semiconductor structure of claim 14, wherein the diffusion barrier layer includes tantalum nitride (TaN).

### Claim 16 (depends on 10)

The semiconductor structure of claim 10, wherein the top surface of the diffusion barrier layer is lower than the top surface of the dielectric layer by about 100 angstroms to about 300 angstroms.

### Claim 17 (depends on 10)

The semiconductor structure of claim 10, wherein the semiconductor structure is a magnetic random access memory (MRAM) cell.

### Claim 18

A semiconductor structure, comprising:
a dielectric layer;
a diffusion barrier layer disposed in the dielectric layer;
a protection layer over the dielectric layer;
a bottom electrode over the diffusion barrier layer; and
a magnetic tunneling junction (MTJ) layer over the bottom electrode;
wherein a lower portion of the bottom electrode is disposed in the dielectric layer, and the MTJ layer and an upper portion of the bottom electrode is disposed in the protection layer, and the diffusion barrier layer and the lower portion of the bottom electrode are laterally in contact with the dielectric layer, and an interface formed by the dielectric layer and the protection layer is level with a bottom surface of the upper portion of the bottom electrode at regions neighboring the bottom surface of the upper portion of the bottom electrode.

### Claim 19 (depends on 18)

The semiconductor structure of claim 18, wherein a top surface of the diffusion barrier layer is lower than a top surface of the dielectric layer by about 100 angstroms to about 300 angstroms.

### Claim 20 (depends on 18)

The semiconductor structure of claim 18, wherein a center region of the top surface of the diffusion barrier layer is higher than an outer region of the top surface of the diffusion barrier layer.