# US 11,114,570 B2 · Memory structure and manufacturing method thereof

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- Number: US 11,114,570 B2
- Document ID: US11114570B2
- Status: Granted
- Kind: B2
- Application number: 16/846,393
- Filed: 2020-04-12
- Published: 2020-10-29
- Granted: 2021-09-07
- Earliest claimed: 2019-04-25
- Assignees: E Ink Holdings Inc.
- Applicants: E Ink Holdings Inc.
- Inventors: Hsiao-Wen Zan; Chuang-Chuang Tsai; Ching-Fu Lin; Zong-Xuan Li; Wei-Tsung Chen
- Web page: https://patentgrep.com/patent/US11114570B2

## CPC

- H10D 30/683: {programmed by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling}
- H10D 30/673: {characterised by the shapes, relative sizes or dispositions of the gate electrodes}
- H10D 30/6739: {Conductor-insulator-semiconductor electrodes}
- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 30/6893: {wherein the floating gate has multiple non-connected parts, e.g. multi-particle floating gate}
- H10D 62/80: characterised by the materials
- H10D 62/814: {Quantum box structures}
- H10D 64/035: {comprising conductor-insulator-conductor-insulator-semiconductor structures}
- H10D 99/00: Subject matter not provided for in other groups of this subclass
- H10P 14/22: using physical deposition, e.g. vacuum deposition or sputtering
- H10P 14/2923: {being conductive materials, e.g. metallic silicides}
- H10P 14/3238: {being insulating materials}
- H10P 14/3241: {being conductive materials}
- H10P 14/3248: {consisting of two layers}
- H10P 14/3256: {Microstructure}
- H10P 14/3426: {Oxides}
- H10P 14/3434: {being oxide semiconductor materials (Group IIB-VIA semiconductor materials H10P14/3424)}
- H10P 14/3461: {Nanoparticles}
- H10P 14/274: {using seed materials}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A memory structure includes a substrate, a gate electrode, a first isolation layer, a thin metal layer, indium gallium zinc oxide (IGZO) particles, a second isolation layer, an IGZO channel layer, and a source/drain electrode. The gate electrode is located on the substrate. The first isolation layer is located on the gate electrode. The thin metal layer is located on the first isolation layer, and has metal particles. The IGZO particles are located on the metal particles. The second isolation layer is located on the IGZO particles. The IGZO channel layer is located on the second isolation layer. The source/drain electrode is located on the IGZO channel layer.

## Claims

### Claim 1

A memory structure, comprising:
a substrate;
a gate electrode located on the substrate;
a first isolation layer located on the gate electrode;
a thin metal layer located on the first isolation layer and having a plurality of metal particles;
a plurality of indium gallium zinc oxide (IGZO) particles located on the metal particles;
a second isolation layer located on the IGZO particles;
an IGZO channel layer located on the second isolation layer; and
a source/drain electrode located on the IGZO channel layer.

### Claim 2 (depends on 1)

The memory structure of claim 1, wherein a thickness of the thin metal layer is in a range from 1 nm to 20 nm.

### Claim 3 (depends on 1)

The memory structure of claim 1, wherein a thickness of each of the IGZO particles is in a range from 2 nm to 20 nm.

### Claim 4 (depends on 1)

The memory structure of claim 1, wherein the thin metal layer is made of a material comprising silver.

### Claim 5 (depends on 1)

The memory structure of claim 1, wherein the IGZO particles are in contact with the thin metal layer.

### Claim 6 (depends on 1)

The memory structure of claim 1, wherein the thin metal layer is in contact with the first isolation layer.

### Claim 7 (depends on 1)

The memory structure of claim 1, wherein the IGZO particles are located between the thin metal layer and the second isolation layer.

### Claim 8

A manufacturing method of a memory structure, the manufacturing method comprising:
forming a thin metal layer on a first isolation layer that is on a gate electrode;
performing a thermal annealing treatment on the thin metal layer such that the thin metal layer has a plurality of metal particles;
forming a indium gallium zinc oxide (IGZO) material on the metal particles such that the IGZO material forms a plurality of IGZO particles;
forming a second isolation layer on the IGZO particles;
forming a IGZO channel layer on the second isolation layer; and
forming a source/drain electrode on the IGZO channel layer.

### Claim 9 (depends on 8)

The manufacturing method of claim 8, wherein forming the thin metal layer on the first isolation layer is performed by thermal evaporation.

### Claim 10 (depends on 8)

The manufacturing method of claim 8, wherein the thermal annealing treatment is performed on the thin metal layer under a temperature in a range from 50° C. to 300° C.

### Claim 11 (depends on 8)

The manufacturing method of claim 8, wherein forming the IGZO material on the metal particles is performed by sputtering.

### Claim 12 (depends on 8)

The manufacturing method of claim 8, wherein a thickness of the thin metal layer is in a range from 1 nm to 20 nm.

### Claim 13 (depends on 8)

The manufacturing method of claim 8, wherein a thickness of each of the IGZO particles is in a range from 2 nm to 20 nm.

### Claim 14 (depends on 9)

The manufacturing method of claim 9, wherein the thin metal layer is made of a material comprising silver.