# US 11,114,568 B2 · Semiconductor device

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 11,114,568 B2
- Document ID: US11114568B2
- Status: Granted
- Kind: B2
- Application number: 16/831,958
- Filed: 2020-03-27
- Published: 2020-07-16
- Granted: 2021-09-07
- Earliest claimed: 2017-04-25
- Assignees: Japan Display Inc.
- Applicants: Japan Display Inc.
- Inventors: Takeshi Sakai; Yuichiro Hanyu; Masahiro Watabe
- Web page: https://patentgrep.com/patent/US11114568B2

## CPC

- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 30/673: {characterised by the shapes, relative sizes or dispositions of the gate electrodes}
- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D 86/0212: {comprising manufacture, treatment or coating of substrates}
- H10D 86/0221: {comprising manufacture, treatment or patterning of TFT semiconductor bodies}
- H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO}
- H10D 86/441: {Interconnections, e.g. scanning lines}
- H10D 86/60: wherein the TFTs are in active matrices
- H10P 14/69215: {the material being a silicon oxide, e.g. SiO2}
- H10P 32/12: between a solid phase and a gaseous phase
- H10P 32/14: within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase
- H10P 32/17: {characterised by the semiconductor material}
- H10P 34/42: with electromagnetic radiation, e.g. laser annealing (laser cutting H10P54/20)
- G02F 1/134363: {for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]}
- G02F 1/1368: in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)}
- G02F 1/13685: {Top gates}
- H10K 59/1213: {the pixel elements being TFTs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES

## Abstract

The purpose of the invention is to form the TFT of the oxide semiconductor, in which influence of variation in mask alignment is suppressed, thus, manufacturing a display device having a TFT of stable characteristics. The concrete measure is as follows. A display device including plural pixels, each of the plural pixels having a thin film transistor (TFT) of an oxide semiconductor comprising: a width of the oxide semiconductor in the channel width direction is wider than a width of the gate electrode in the channel width direction.

## Claims

### Claim 1

A semiconductor device having a thin film transistor (TFT) comprising an oxide semiconductor layer, a drain electrode, a source electrode, a gate insulating film, a gate electrode, and a channel, which is formed in the oxide semiconductor layer between the drain electrode and the source electrode,
a channel length direction is defined by a direction the drain electrode and the source electrode oppose to each other,
a channel width direction is defined by an orthogonal direction to the channel length direction,
wherein a width of the oxide semiconductor layer in the channel width direction is wider than a width of the gate electrode in the channel width direction,
a width of the drain electrode and a width of the source electrode in the channel width direction are wider than the width of the oxide semiconductor layer in the channel width direction, and
wherein the gate insulating film is formed between the gate electrode and the oxide semiconductor layer,
the oxide semiconductor layer that is not covered by the gate electrode is covered by a silicon oxide film in addition to the gate insulating film.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1,
wherein the oxide semiconductor layer has an area that does not overlap the gate electrode at both sides of the gate electrode in channel width direction.

### Claim 3

A semiconductor device having a thin film transistor (TFT) comprising an oxide semiconductor layer, a drain electrode, a source electrode, a gate insulating film, a gate electrode, and a channel, which is formed in the oxide semiconductor layer between the drain electrode and the source electrode,
a channel length direction is defined by a direction the drain electrode and the source electrode oppose to each other,
a channel width direction is defined by an orthogonal direction to the channel length direction,
wherein a width of the oxide semiconductor layer in the channel width direction is wider than a width of the gate electrode in the channel width direction,
wherein a resistivity of the oxide semiconductor layer in the area that does not overlap the gate electrode is bigger than a resistivity of the oxide semiconductor layer in the area that overlaps the gate electrode,
a width of the drain electrode and a width of the source electrode in the channel width direction are wider than the width of the oxide semiconductor layer in the channel width direction, and
wherein the gate insulating film is formed between the gate electrode and the oxide semiconductor layer,
the oxide semiconductor layer that is not covered by the gate electrode is covered by a silicon oxide film in addition to the gate insulating film.

### Claim 4 (depends on 3)

The semiconductor device according to claim 3,
wherein the oxide semiconductor layer has an area that does not overlap the gate electrode at both sides of the gate electrode in channel width direction.

### Claim 5

A semiconductor device having a thin film transistor (TFT) comprising an oxide semiconductor layer, a drain electrode, a source electrode, a gate insulating film, a gate electrode, and a channel, which is formed in the oxide semiconductor layer between the drain electrode and the source electrode,
a channel length direction is defined by a direction the drain electrode and the source electrode oppose to each other,
a channel width direction is defined by an orthogonal direction to the channel length direction,
wherein a width of the oxide semiconductor layer in the channel width direction is wider than a width of the gate electrode in the channel width direction,
a width of the drain electrode and a width of the source electrode in the channel width direction are wider than the width of the oxide semiconductor layer in the channel width direction,
wherein the drain electrode and the source electrode of the TFT are formed on a lower layer than the gate electrode of the TFT, and
wherein the drain electrode and the source electrode directly contact the oxide semiconductor layer of the TFT without a through hole, and
wherein the gate insulating film is formed between the gate electrode and the oxide semiconductor layer,
the oxide semiconductor layer that is not covered by the gate electrode is covered by a silicon oxide film in addition to the gate insulating film.

### Claim 6 (depends on 5)

The semiconductor device according to claim 5,
wherein the oxide semiconductor layer has an area that does not overlap the gate electrode at both sides of the gate electrode in channel width direction.