# US 11,114,567 B2 · Manufacturing method of TFT substrate and TFT substrate

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- Number: US 11,114,567 B2
- Document ID: US11114567B2
- Status: Granted
- Kind: B2
- Application number: 16/278,718
- Filed: 2019-02-19
- Published: 2019-06-13
- Granted: 2021-09-07
- Earliest claimed: 2016-05-23
- Assignees: Shenzhen China Star Optoelectronics Technology Co., Ltd.
- Applicants: Shenzhen China Star Optoelectronics Technology Co., Ltd.
- Inventors: Zhichao Zhou; Hui Xia
- Web page: https://patentgrep.com/patent/US11114567B2

## CPC

- H10D 30/6728: {Vertical TFTs}
- H10D 30/031: {of thin-film transistors [TFT]}
- H10D 30/0312: {characterised by the gate electrodes}
- H10D 30/0318: {of vertical TFTs}
- H10D 30/0321: {comprising silicon, e.g. amorphous silicon or polysilicon}
- H10D 30/6734: {having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs}
- H10D 30/6739: {Conductor-insulator-semiconductor electrodes}
- H10D 64/011: {of electrodes ohmically coupled to a semiconductor}
- H10D 64/01332: {Making the insulator}
- H10D 86/0212: {comprising manufacture, treatment or coating of substrates}
- H10D 86/0221: {comprising manufacture, treatment or patterning of TFT semiconductor bodies}
- H10D 86/0231: {using masks, e.g. half-tone masks}
- H10D 86/421: {having a particular composition, shape or crystalline structure of the active layer}
- H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO}
- H10D 86/441: {Interconnections, e.g. scanning lines}
- H10D 86/60: wherein the TFTs are in active matrices
- H10D 99/00: Subject matter not provided for in other groups of this subclass
- H10P 14/418: {the conductive layers comprising transition metals}
- H10P 14/6334: {using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition (deposition by physical ablation of a target H10P14/6329)}
- H10P 50/282: {of inorganic materials}
- H10P 50/283: {by chemical means}
- H10P 50/642: {Chemical etching}
- H10P 50/667: {by liquid etching only}
- H10P 50/69: {using masks for semiconductor materials}
- H10P 50/692: {characterised by their composition, e.g. multilayer masks or materials}
- H10P 50/71: {using masks for conductive or resistive materials}
- H10P 50/73: {using masks for insulating materials}
- H10P 76/2041: {Photolithographic processes}
- H10P 95/00: Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
- H10W 74/137: {the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence)}
- H10P 14/69215: {the material being a silicon oxide, e.g. SiO2}
- H10P 14/69433: {the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A manufacturing method of TFT substrate and a TFT substrate are provided. The method provides a dual-gate structure symmetrically disposed on both sides of active layer, which prevents TFT threshold voltage from changing and improve TFT conduction state switching; by first manufacturing the active layer before the gate insulating layer to make the insulating layer directly grow on active layer, the contact interface between the gate insulating layer and active layer is improved, leading to further improving TFT conduction state switching. The TFT substrate makes the gate located between the source and the pixel electrode in vertical direction, and the dual-gate is symmetrically disposed on both sides of active layer to prevent TFT threshold voltage from changing and improve TFT conduction state switching, as well as improve the contact interface between the gate insulating layer and active layer, leading to further improving TFT conduction state switching.

## Claims

### Claim 1

A manufacturing method of thin film transistor (TFT) substrate, which comprises:
Step 1: providing a base substrate, and forming a data line and a source connected to the data line on the base substrate;
Step 2: forming an active layer, the active layer being at least partially above the source;
Step 3: forming a gate insulating layer on top of the active layer, the source, the data line and the base substrate such that a portion of the gate insulating layer is directly formed on the top of the active layer to completely cover and directly contact entirety of the top of the active layer, and patternizing the gate insulating layer to form a first via corresponding to the active layer;
Step 4: forming a first gate, a second gate and a drain, the first gate and the second gate being on the gate insulating layer and corresponding respectively to two lateral sides of the active layer, the drain being at least partially inside the first via and connected to the active layer through the first via;
Step 5: forming a passivation layer on the drain, the first gate, the second gate and the gate insulating layer, patternizing the passivation layer to form a second via corresponding to the drain; and
Step 6: forming a pixel electrode, the pixel electrode being at least partially inside the second via and connected to the drain through the second via,
wherein the drain is formed after the formation of the gate insulating layer and is filled in the first via of the gate insulating layer such that the connection between drain and the active layer is formed after the formation of the gate insulating layer; and
wherein the second via is located above and corresponding, in position, to the first via such that the second via is communication with the first via and a part of the pixel electrode that is located in the second via is in direct, electrical contact with a part of the drain that is located in the first via and an orthographic projection that is cast by the part of the pixel electrode located in the second via on the base substrate completely covers orthographic projections that are respectively cast by the part of drain located in the first via and the active layer on the base substrate.

### Claim 2 (depends on 1)

The manufacturing method of TFT substrate as claimed in claim 1, wherein Step 1 further comprises: depositing a first metal layer on the base substrate by physical vapor deposition, and using a lithography process to patternize the first metal layer to obtain the data line and the source connected to the data line; the lithography process comprising: photo-resist coating, exposure, development, and wet etching process;
Step 2 further comprises: depositing a semiconductor layer on the base substrate, data line and source by chemical or physical vapor deposition, and using a lithography process to patternize the semiconductor layer to obtain the active layer; the lithography process comprising: photo-resist coating, exposure, development, and wet etching process;
the data line and the source are made of one or more of the following: molybdenum, titanium, aluminum, copper; and
the active layer is made of amorphous silicon, polysilicon, or a metal oxide semiconductor.

### Claim 3 (depends on 1)

The manufacturing method of TFT substrate as claimed in claim 1, wherein Step 3 further comprises: depositing a first insulating layer on the active layer, source, data line and base substrate by chemical vapor deposition, and using a lithography process to patternize the first insulating layer to obtain the first via corresponding to the active layer to form the gate insulating layer; the lithography process comprising: photo-resist coating, exposure, development, and wet etching process;
the gate insulating layer is made of one or more of silicon oxide, and silicon nitride.

### Claim 4 (depends on 1)

The manufacturing method of TFT substrate as claimed in claim 1, wherein Step 4 further comprises: depositing a second metal layer on the gate insulating layer by physical vapor deposition, and using a lithography process to patternize the second metal layer to obtain the drain, the first gate and the second gate; the lithography process comprising: photo-resist coating, exposure, development, and wet etching process;
the drain, the first gate and the second gate are made of one or more of the following: molybdenum, titanium, aluminum, copper.