# US 11,114,566 B2 · Semiconductor device and method of manufacturing the same

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- Number: US 11,114,566 B2
- Document ID: US11114566B2
- Status: Granted
- Kind: B2
- Application number: 16/033,256
- Filed: 2018-07-12
- Published: 2020-01-16
- Granted: 2021-09-07
- Earliest claimed: 2018-07-12
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Zhi-Chang Lin; Kai-Chieh Yang; Chia-Wei Su; Jia-Ni Yu; Wei-Hao Wu; Chih-Hao Wang
- Web page: https://patentgrep.com/patent/US11114566B2

## CPC

- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/0243: {using dummy structures having essentially the same shapes as the semiconductor bodies, e.g. to provide stability}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10P 14/6339: {deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD}
- H10P 14/6903: {containing silicon}
- H10P 50/00: Etching of wafers, substrates or parts of devices
- H10W 10/011: {of isolation regions comprising dielectric materials}
- H10W 10/10: Isolation regions comprising dielectric materials
- H10W 20/48: Insulating materials thereof
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a substrate, a first fin, a second fin, a dummy fin, a first metal gate, a second metal gate, and an isolation structure. The first, the second and the dummy fins are on the substrate, and the dummy fin is disposed between the first fin and the second fin. The first metal gate and the second metal gate are over the first fin and the second fin, respectively. The isolation structure is on the dummy fin, and the dummy fin and the isolation structure separate the first metal gate and the second metal gate.

## Claims

### Claim 1

A semiconductor device comprising:
a first fin, a second fin and a dummy fin arranged on a substrate along a first direction, wherein the dummy fin is disposed between the first fin and the second fin;
a first epitaxial source/drain region over the first fin;
a first metal gate over the first fin and a second metal gate over the second fin;
an isolation structure on the dummy fin, wherein the dummy fin and the isolation structure separate the first and the second metal gate; and
a metal wire in direct contact with a top surface and opposite sidewalls of the dummy fin and extending over the first epitaxial source/drain region along the first direction.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the isolation structure covers a portion of at least one sidewall of the dummy fin.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the isolation structure has a width that is greater than a width of the dummy fin.

### Claim 4

A semiconductor device comprising:
a first fin, a second fin, and a dummy fin on a substrate and extending along a first direction, wherein the dummy fin is disposed between the first and the second fins;
a first and a second metal gate respectively on the first and the second fins;
a third and a fourth metal gate respectively on the first and second fins;
a first isolation structure over the dummy fin and between the first and the second metal gate, wherein the first isolation structure, the first and the second metal gate are aligned in a second direction, which is perpendicular to the first direction;
a second isolation structure over the dummy fin and between the third and the fourth metal gate, wherein the second isolation structure is next to the first isolation structure, and the second isolation structure, the third and the fourth metal gate are aligned in the second direction;
a first and a second epitaxial source/drain (S/D) region respectively on the first and the second fin;
an interlayer dielectric (ILD) layer over the first and the second epitaxial source/drain (S/D) region; and
a metal wire in contact with a top surface of the dummy fin, wherein the metal wire is laterally between the first isolation structure and the second isolation structure along the first direction, and wherein a bottommost surface of the metal wire is higher than a bottommost surface of the first metal gate.

### Claim 5 (depends on 4)

The semiconductor device of claim 4, wherein the dummy fin comprises SiO, SiN, SiON, SiOCN, hafnium silicon oxide, zirconium silicon oxide, aluminum silicon oxide, or a combination of thereof.

### Claim 6 (depends on 4)

The semiconductor device of claim 4, wherein the first isolation structure has a width that is greater than a width of the dummy fin.

### Claim 7 (depends on 6)

The semiconductor device of claim 6, wherein the first isolation structure overlaps a portion of opposite sidewalls of the dummy fin.

### Claim 8 (depends on 4)

The semiconductor device of claim 4, wherein the first isolation structure overlaps a portion of a sidewall of the dummy fin.

### Claim 9

A semiconductor device comprising:
a first semiconductor fin and a second semiconductor fin on a substrate;
a dummy fin disposed on the substrate and between the first semiconductor fin and the second semiconductor fin;
a first metal gate crossing the first semiconductor fin and a second metal gate crossing the second semiconductor fin;
an isolation structure on and overlapped with the dummy fin, wherein the isolation structure is aligned with the first metal gate and the second metal gate along a lengthwise direction of the first metal gate and the second metal gate, wherein the dummy fin and the isolation structure separates the first metal gate from the second metal gate, and wherein along the lengthwise direction of the first metal gate and the second metal gate, the isolation structure is closer to the second semiconductor fin than to the first semiconductor fin, and the first metal gate extends to a top surface of the dummy fin;
an interlayer dielectric (ILD) layer adjacent to the isolation structure; and
a metal wire in the ILD layer.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, wherein the isolation structure has a width that is greater than a width of the dummy fin.

### Claim 11 (depends on 9)

The semiconductor device of claim 9, wherein the isolation structure overlaps a portion of a sidewall of the dummy fin.

### Claim 12 (depends on 9)

The semiconductor device of claim 9, wherein the isolation structure overlaps a portion of opposite sidewalls of the dummy fin.

### Claim 13 (depends on 9)

The semiconductor device of claim 9, wherein the isolation structure has a bottom surface coplanar with a top surface of the dummy fin.

### Claim 14 (depends on 9)

The semiconductor device of claim 9, further comprising a plurality of epitaxial source/drain (S/D) region respectively on the first and second semiconductor fins.

### Claim 15 (depends on 9)

The semiconductor device of claim 9, further comprising a metal wire crossing the first and second semiconductor fins and the dummy fin.

### Claim 16 (depends on 9)

The semiconductor device of claim 9, wherein a bottom surface of the isolation structure is lower than a top surface of the dummy fin, and is in contact with the first and second metal gates.

### Claim 17 (depends on 1)

The semiconductor device of claim 1, wherein the isolation structure covers at least three sides of the dummy fin.

### Claim 18 (depends on 1)

The semiconductor device of claim 1, wherein a top surface of the metal wire is substantially level with a top surface of the first metal gate, and a bottommost surface of the metal wire is higher than a bottommost surface of the first metal gate.

### Claim 19 (depends on 9)

The semiconductor device of claim 9, wherein a bottommost surface of the metal wire is higher than a bottommost surface of the first metal gate.

### Claim 20 (depends on 9)

The semiconductor device of claim 9, wherein the metal wire is in direct contact with a top surface and opposite sidewalls of the dummy fin.