# US 11,114,565 B2 · Semiconductor device

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- Number: US 11,114,565 B2
- Document ID: US11114565B2
- Status: Granted
- Kind: B2
- Application number: 16/650,928
- Filed: 2018-09-11
- Published: 2020-07-30
- Granted: 2021-09-07
- Earliest claimed: 2017-09-29
- Assignees: National Institute of Advanced Industrial Science and Technology
- Applicants: National Institute of Advanced Industrial Science and Technology
- Inventors: Hiroyuki Ota; Shinji Migita
- Web page: https://patentgrep.com/patent/US11114565B2

## CPC

- H10D 30/701: {IGFETs having ferroelectric gate insulators, e.g. ferroelectric FETs}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10B 51/30: characterised by the memory core region
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/0415: {of FETs having ferroelectric gate insulators}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/67: Thin-film transistors [TFT] {(Stacked nanowire, nanosheet or nanoribbon FETs H10D30/501)}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/121: {oriented parallel to substrates}
- H10D 64/033: {comprising ferroelectric layers}
- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10D 64/689: {having ferroelectric layers}
- H10D 84/832: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 84/834: {comprising FinFETs}
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/425: {Barrier, adhesion or liner layers}
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H10W 20/48: Insulating materials thereof
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/6744: {Monocrystalline silicon}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- H10B: ELECTRONIC MEMORY DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Power consumption of a semiconductor device is reduced by sharpening the rise of a drain current when a gate voltage of a field effect transistor is less than a threshold voltage. As means therefor, in a fully-depleted MOSFET in which a thickness of a semiconductor layer serving as a channel region is 20 nm or less, a gate plug connected to a gate electrode is constituted of a first plug, a ferroelectric film, and a second plug sequentially stacked on the gate electrode. Here, an area where a contact surface between the first plug and the ferroelectric film and a contact surface between the ferroelectric film and the second plug overlap in a plan view is smaller than an area where the gate electrode and a semiconductor layer serving as an active region overlap.

## Claims

### Claim 1

A semiconductor device comprising:
a semiconductor layer having a thickness of 20 nm or less;
a gate electrode formed over the semiconductor layer via a gate insulating film;
a pair of source/drain regions in which an impurity of a first conductivity type is introduced into the semiconductor layer next to the gate electrode;
a first plug electrically connected to the gate electrode;
a ferroelectric film connected to an upper surface of the first plug; and
a second plug connected to an upper surface of the ferroelectric film,
wherein the gate electrode and the source/drain regions constitute a first field effect transistor, and
a first area where a contact surface between the first plug and the ferroelectric film and a contact surface between the ferroelectric film and the second plug overlap in a plan view is smaller than a second area where the gate electrode and the semiconductor layer overlap.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, further comprising:
a semiconductor substrate; and
a first insulating film over the semiconductor substrate,
wherein the semiconductor layer is formed over the first insulating film.

### Claim 3

A semiconductor device comprising:
a semiconductor substrate;
a protruding portion which is part of the semiconductor substrate, protrudes upward from an upper surface of the semiconductor substrate, and extends in a first direction along the upper surface of the semiconductor substrate;
a gate electrode which is formed over an upper surface of the protruding portion via a gate insulating film and extends in a second direction orthogonal to the first direction;
a pair of source/drain regions of a first conductivity type formed in a surface of the protruding portion so as to sandwich the protruding portion immediately below the gate electrode in the first direction;
a first plug electrically connected to the gate electrode;
a ferroelectric film connected to an upper surface of the first plug; and
a second plug connected to an upper surface of the ferroelectric film,
wherein the gate electrode and the source/drain regions constitute a field effect transistor,
a width of the protruding portion in the second direction is 20 nm or less, and
a first area where a contact surface between the first plug and the ferroelectric film and a contact surface between the ferroelectric film and the second plug overlap in a plan view is smaller than a second area where the gate electrode covers the protruding portion.

### Claim 4 (depends on 3)

The semiconductor device according to claim 3,
wherein a dielectric film is interposed between the first plug and the ferroelectric film or between the ferroelectric film and the second plug.

### Claim 5 (depends on 4)

The semiconductor device according to claim 4,
wherein the dielectric film is made of an oxide film of Ti or Zr or an Hf oxide film whose crystal structure is trimetric, cubic, or tetragonal.

### Claim 6 (depends on 3)

The semiconductor device according to claim 3,
wherein the ferroelectric film contains orthorhombic HfO2.

### Claim 7 (depends on 6)

The semiconductor device according to claim 6,
wherein Y, Zr, N, Al, Gd, Sr, La, or Si is added to the ferroelectric film.

### Claim 8 (depends on 3)

The semiconductor device according to claim 3,
wherein a metal film containing TiN, TaN, Pt, or SrRuO3 is interposed between the first plug and the ferroelectric film or between the ferroelectric film and the second plug.

### Claim 9 (depends on 3)

The semiconductor device according to claim 3, further comprising an interlayer insulating film formed over the gate electrode and having a connection hole penetrating from an upper surface to a lower surface,
wherein the ferroelectric film covers a bottom surface and a side surface of the connection hole, and
the connection hole is filled with the ferroelectric film and the second plug.

### Claim 10

A semiconductor device comprising:
a semiconductor substrate;
a first insulating film over the semiconductor substrate;
a cylindrical first semiconductor layer formed over the first insulating film and extending in a first direction along an upper surface of the semiconductor substrate;
a gate electrode surrounding a periphery of the first semiconductor layer in a diameter direction via a first gate insulating film;
a pair of source/drain regions which is connected to both ends of the first semiconductor layer in an extending direction, respectively, and to which an impurity of a first conductivity type is introduced;
a first plug electrically connected to the gate electrode;
a ferroelectric film connected to an upper surface of the first plug; and
a second plug connected to an upper surface of the ferroelectric film,
wherein the gate electrode and the source/drain regions constitute a first field effect transistor, and
a first area where a contact surface between the first plug and the ferroelectric film and a contact surface between the ferroelectric film and the second plug overlap in a plan view is smaller than a second area where the gate electrode covers the first semiconductor layer.

### Claim 11 (depends on 10)

The semiconductor device according to claim 10, further comprising a second semiconductor layer formed over the first semiconductor layer so as to be separated from the first semiconductor layer,
wherein the second semiconductor layer has a cylindrical structure extending in the first direction,
both ends of the second semiconductor layer are connected to the pair of source/drain regions, respectively, and
a periphery of the second semiconductor layer in a diameter direction is surrounded by the gate electrode via a second gate insulating film.