# US 11,114,563 B2 · Semiconductor devices with low junction capacitances and methods of fabrication thereof

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- Number: US 11,114,563 B2
- Document ID: US11114563B2
- Status: Granted
- Kind: B2
- Application number: 15/942,639
- Filed: 2018-04-02
- Published: 2018-08-09
- Granted: 2021-09-07
- Earliest claimed: 2009-02-24
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Cheng-Hung Chang; Yu-Rung Hsu; Chen-Hua Yu
- Web page: https://patentgrep.com/patent/US11114563B2

## CPC

- H10D 30/601: {having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs (lightly doped source or drain extensions for TFTs H10D30/6715)}
- H10D 30/681: {having only two programming levels (Floating gate IGFETs programmable by two single electrons H10D30/688)}
- H10D 30/69: IGFETs having charge trapping gate insulators, e.g. MNOS transistors
- H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 84/0188: {Manufacturing their isolation regions}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 86/01: Manufacture or treatment
- H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)}
- H10D 87/00: Integrated devices comprising both bulk components and either SOI or SOS components on the same substrate
- H10D 30/0227: {having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET}
- H10D 64/015: {removing at least parts of gate spacers, e.g. disposable spacers}
- H10P 90/1906: {Preparing SOI wafers}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/061: {using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10W 10/181: {Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Semiconductor devices with low junction capacitances and methods of fabrication thereof are described. In one embodiment, a method of forming a semiconductor device includes forming isolation regions in a substrate to form active areas. The sidewalls of the active areas are enclosed by the isolation regions. The isolation regions are recessed to expose first parts of the sidewalls of the active areas. The first parts of the sidewalls of the active areas are covered with spacers. The isolation regions are etched to expose second parts of the sidewalls of the active area, the second parts being disposed below the first parts. The active areas are etched through the exposed second parts of the sidewalls to form lateral openings. The lateral openings are filled with a spin on dielectric.

## Claims

### Claim 1

A semiconductor device comprising:
a substrate;
an active area in the substrate, the active area, when viewed in cross section, having
a lower portion with a first width laterally bounded on a first side and a second side by a first dielectric layer and a second dielectric layer, respectively,
a mid portion, above the lower portion, the mid portion having a second width laterally bounded by a third dielectric layer and a fourth dielectric layer, respectively, the second width being less than the first width and the third and fourth dielectric layers at least partially disposed over the first and second dielectric layers, the third and fourth dielectric layers being distinct layers from the first and second dielectric layers, and
a channel portion, the channel portion having a third width bounded by a first source/drain region and a second source/drain region, respectively, the third width being less than the second width, wherein the lower portion, the mid portion, and the channel portion are a continuous semiconductor region;
a gate structure formed, at least in part, above the channel portion; and
spacers on opposing sides of the channel portion, the spacers being separated from the active area by the third dielectric layer and the fourth dielectric layer.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein a width of the channel portion is less than a smallest width of the mid portion.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein sidewalls of the third dielectric layer are convex.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the active area extends below the first source/drain region and the second source/drain region.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the active area extends above at least portions of the first dielectric layer and the second dielectric layer.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein a thickness of the third dielectric layer and the fourth dielectric layer is between about 10 nm to about 150 nm.

### Claim 7

A semiconductor device comprising:
a substrate;
a first dielectric layer;
a first active area bounded laterally by the first dielectric layer, the first active area having a first thickness;
a second active area bounded laterally by the first dielectric layer, the first active area being laterally offset from the second active area, the second active area having a second thickness different than the first thickness, the first dielectric layer extending under each of the first active area and the second active area, top surfaces of the first active area and the second active area being at a same level; and
a second dielectric layer below the first dielectric layer, the substrate being interposed between portions of the second dielectric layer.

### Claim 8 (depends on 7)

The semiconductor device of claim 7, wherein the first active area comprises a first source/drain region, wherein the second active area comprises a second source/drain region, and wherein the first dielectric layer extends immediately below the second source/drain region.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, wherein the first source/drain region is spaced apart from the first dielectric layer.

### Claim 10 (depends on 7)

The semiconductor device of claim 7, further comprising a first gate electrode over the first active area, wherein a width of the first gate electrode is less than a width of a first portion of the substrate, the first portion being laterally below the first gate electrode, the first portion being laterally bounded by portions of the second dielectric layer.

### Claim 11 (depends on 10)

The semiconductor device of claim 10, further comprising a second gate electrode over the second active area, wherein a width of the second gate electrode is less than a width of a second portion of the substrate, the second portion being laterally below the second gate electrode, the second portion being laterally bounded by portions of the second dielectric layer.

### Claim 12

A semiconductor device comprising:
a substrate;
an active area in the substrate, the active area comprising:
a lower portion with a first width laterally bounded by a first dielectric material,
an upper portion with a second width laterally bounded by a second dielectric material, the upper portion including a source region, a drain region, and a channel region, the second dielectric material having a lower surface disposed on an upper surface of the first dielectric material, and
a mid portion interposed between the lower portion and the upper portion, the mid portion having a third width, the third width being a narrowest width laterally bounded by the second dielectric material, the third width being less than the first width and the second width;
a gate structure formed, at least in part, above the upper portion; and
a dielectric spacer on opposing sides of the upper portion, the dielectric spacer being separated from the active area by the second dielectric material.

### Claim 13 (depends on 12)

The semiconductor device of claim 12, wherein a width of the channel region is less than the third width.

### Claim 14 (depends on 12)

The semiconductor device of claim 12, wherein a width of the mid portion increases as the mid portion extends toward the lower portion.

### Claim 15 (depends on 12)

The semiconductor device of claim 12, wherein the mid portion is laterally bounded by a first dielectric layer, the lower portion is laterally bounded by a second dielectric layer different than the first dielectric layer.

### Claim 16 (depends on 12)

The semiconductor device of claim 12, wherein the upper portion and the mid portion are laterally bounded by a same dielectric layer.

### Claim 17 (depends on 12)

The semiconductor device of claim 12, wherein a thickness of the upper portion in the source region increases as the upper portion extends away from the channel region.

### Claim 18 (depends on 12)

The semiconductor device of claim 12, wherein sidewalls of the second dielectric material are convex.

### Claim 19 (depends on 12)

The semiconductor device of claim 12, wherein the dielectric spacer surrounds the upper portion.

### Claim 20 (depends on 12)

The semiconductor device of claim 12, wherein the second dielectric material extends below the source region and the drain region.