# US 11,114,561 B2 · LDMOS device and method for manufacturing same

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- Number: US 11,114,561 B2
- Document ID: US11114561B2
- Status: Granted
- Kind: B2
- Application number: 16/569,135
- Filed: 2019-09-12
- Published: 2020-04-02
- Granted: 2021-09-07
- Earliest claimed: 2018-09-29
- Assignees: Shanghai Huahong Grace Semiconductor Manufacturing Corporation
- Applicants: Shanghai Huahong Grace Semiconductor Manufacturing Corporation
- Inventors: Zhaozhao Xu
- Web page: https://patentgrep.com/patent/US11114561B2

## CPC

- H10D 30/603: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]}
- H10D 30/655: {having edge termination structures}
- H10D 30/0212: {using self-aligned silicidation}
- H10D 30/0221: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]}
- H10D 30/0281: {of lateral DMOS [LDMOS] FETs}
- H10D 62/154: {Dispositions}
- H10D 62/158: {Dispositions}
- H10D 62/235: {of IGFETs (IGFETs having buried channels H10D30/637)}
- H10D 62/371: {Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 64/01: Manufacture or treatment
- H10D 64/0131: {the additional conductive layer comprising a silicide layer formed by the silicidation reaction between the layer of silicon with a metal layer which is not formed by metal implantation}
- H10D 64/111: {Field plates}
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10D 64/663: {the additional layers comprising a silicide layer contacting the layer of silicon, e.g. polycide gates}
- H10P 30/204: {into Group IV semiconductors}
- H10P 30/21: {of electrically active species}
- H10P 50/264: {by chemical means}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

LDMOS device including a drift region, a body region, a gate dielectric layer, a polysilicon gate, a source region, a drain region and a common dielectric layer, the common dielectric layer covers a portion, between a second side of the polysilicon gate and the drain region, of the surface of the drift region, extends onto the surface of the polysilicon gate and also covers part of the surface of the drain region, a self-aligned metal silicide is formed on portions, not covered by the common dielectric layer, of the surfaces of the polysilicon gate, the source region and the drain region, and the common dielectric layer serves as a growth barrier layer of the self-aligned metal silicide; a drain terminal field plate is formed on a portion of the surface of the common dielectric layer; and a portion of the common dielectric layer serves as a field plate dielectric layer.

## Claims

### Claim 1

A LDMOS device, comprising:
a first epitaxial layer of a second conduction type, wherein a drift region of a first conduction type and a body region of a second conduction type are formed in selected areas of the first epitaxial layer, and the drift region horizontally makes contact with the body region or is spaced from the body region by a certain distance, the first epitaxial layer is a silicon epitaxial layer;
a gate structure which is formed on a surface of the body region by stacking a gate dielectric layer and a polysilicon gate, wherein channels are formed on the surface, covered by the polysilicon gate, of the body region, and a second side of the gate dielectric layer and a second side of the polysilicon gate extend onto a surface of the drift region;
a source region which is formed on the surface of the body region and has a second side self-aligned with a first side of the polysilicon gate;
a drain region which is formed in a selected area of the drift region and has a first side spaced from the second side of the polysilicon gate by a certain distance; and
a common dielectric layer, wherein the common dielectric layer covers a portion, between the second side of the polysilicon gate and the drain region, of the surface of drift region, extends onto a surface of the polysilicon gate and also covers part of a surface of the drain region, a self-aligned metal silicide is formed on portions, not covered by the common dielectric layer, of the surfaces of the polysilicon gate, the source region and the drain region, and the common dielectric layer serves a growth barrier layer of the self-aligned metal silicide; and
a drain terminal field plate is formed on a portion, between the second side of the polysilicon gate and the drain region, of a surface of the common dielectric layer, and a portion, located at a bottom of the drain terminal field plate, of the common dielectric layer serves as a field plate dielectric layer;
the drain terminal field plate comprises a second polysilicon layer or a self-aligned metal silicide formed through self-aligned metal silicification on a surface of the second polysilicon layer;
the polysilicon gate is connected to a gate electrode formed by a front metal layer via the contact hole at the top of the polysilicon gate, and the drain terminal field plate is also connected to the gate electrode formed by the front metal layer via the contact hole at the top of the drain terminal field plate.

### Claim 2 (depends on 1)

The LDMOS device according to claim 1, wherein a first doped buried layer of the first conduction type is formed at a bottom of the first epitaxial layer and is located on a surface of a semiconductor substrate.

### Claim 3 (depends on 2)

The LDMOS device according to claim 2, wherein the semiconductor substrate is a silicon substrate;
the gate dielectric layer is made from silicon oxide; and
the common dielectric layer is made from silicon oxide.

### Claim 4 (depends on 1)

The LDMOS device according to claim 1, wherein a heavily-doped body lead-out region of the second conduction type is formed on the surface of the body region and makes contact a side face of a first side of the source region, and the self-aligned metal silicide on the surface of the source region extends onto the surface of the body lead-out region.

### Claim 5 (depends on 1)

The LDMOS device according to claim 1, wherein the LDMOS device further comprises:
a contact hole etching stop layer, an interlayer film, contact holes and a front metal layer, wherein:
the contact holes penetrate through the corresponding interlayer film and the contact hole etching stop layer and make contact with the self-aligned metal silicide at bottoms of the contact holes; and
the corresponding contact holes are formed at tops of the source region, the drain region, the polysilicon gate and the drain terminal field plate, the source region is connected to a source electrode formed by the front metal layer via the contact hole at the top of the source region, the drain region is connected to a drain electrode formed by the front metal layer via the contact hole at the top of the drain region.

### Claim 6 (depends on 5)

The LDMOS device according to claim 5, wherein the contact hole etching stop layer is formed by stacking an oxide layer and a nitride layer; and
the interlayer film is formed by an oxide layer.

### Claim 7 (depends on 1)

The LDMOS device according to claim 1, wherein a spacer is formed on a side face of the polysilicon gate.

### Claim 8 (depends on 1)

The LDMOS device according to claim 1, if a thickness of the second polysilicon layer is decreased to be smaller than 200 Å, the second polysilicon layer is completely converted into the self-aligned metal silicide, and in this case, the drain terminal field plate is completely formed by the self-aligned metal silicide; and
if the second polysilicon layer is not completely converted into the self-aligned metal silicide, the drain terminal field plate is formed by stacking the rest of the second polysilicon layer and the self-aligned metal silicide on the surface of the second polysilicon layer.