# US 11,114,555 B2 · High electron mobility transistor device and methods for forming the same

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- Number: US 11,114,555 B2
- Document ID: US11114555B2
- Status: Granted
- Kind: B2
- Application number: 16/545,230
- Filed: 2019-08-20
- Published: 2021-02-25
- Granted: 2021-09-07
- Earliest claimed: 2019-08-20
- Assignees: Vanguard International Semiconductor Corporation
- Applicants: Vanguard International Semiconductor Corporation
- Inventors: Chi-Feng Hsieh; Tuan-Wei Wang; Chien-Jen Sun
- Web page: https://patentgrep.com/patent/US11114555B2

## CPC

- H10D 30/475: {having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs}
- H10D 30/4755: {having wide bandgap charge-carrier supplying layers, e.g. modulation doped HEMTs such as n-AlGaAs/GaAs HEMTs}
- H10D 30/015: {of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT}
- H10P 14/3216: {Nitrides}
- H10P 14/3252: {Alternating layers, e.g. superlattice}
- H10P 14/3254: {Graded layers}
- H10P 14/3406: {Carbon, e.g. diamond-like carbon}
- H10P 14/3416: {Nitrides}
- H10P 14/3444: {P-type}
- H10P 14/69391: {the material containing aluminium, e.g. Al2O3}
- H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN}
- H10D 62/854: further characterised by the dopants
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A high electron mobility transistor device includes a substrate, a plurality of pairs of alternating layers, at least one stress-relief layer and a gallium nitride layer. The plurality of pairs of alternating layers is disposed over the substrate, and each pair of alternating layers includes a carbon-doped gallium nitride layer and an undoped gallium nitride layer. The stress-relief layer is disposed between the pairs of alternating layers. The gallium nitride layer is disposed over the alternating layers.

## Claims

### Claim 1

A high electron mobility transistor device, comprising:
a substrate;
a buffer layer disposed over the substrate, wherein the buffer layer comprises a gradient buffer layer disposed over a superlattice buffer layer, and wherein the superlattice buffer layer comprises a plurality of pairs of AlN layers and AlGaN layers, the gradient buffer layer comprises a plurality of AlGaN layers with different concentrations, and one of the plurality of AlGaN layers of the gradient buffer layer is in contact with one of the AlN layers of the superlattice buffer layer;
a plurality of pairs of alternating layers disposed over the substrate buffer layer, wherein each pair of alternating layers comprises a carbon-doped gallium nitride layer and an undoped gallium nitride layer, and a topmost layer of the pairs of alternating layers is a topmost undoped gallium nitride layer;
a stress-relief layer disposed over the topmost undoped gallium nitride layer;
a gallium nitride layer disposed over the stress-relief layer, wherein the stress-relief layer is in contact with the gallium nitride layer and the topmost undoped gallium nitride layer; and
a barrier layer disposed over the gallium nitride layer, wherein a 2DEG is created at the interface between the gallium nitride layer and the barrier layer.

### Claim 2 (depends on 1)

The high electron mobility transistor device as claimed in claim 1, wherein the stress-relief layer is an aluminum-containing layer.

### Claim 3 (depends on 2)

The high electron mobility transistor device as claimed in claim 2, wherein the aluminum-containing layer comprises aluminum nitride (AlN), aluminum gallium nitride (AlGaN), or a combination thereof.

### Claim 4 (depends on 1)

The high electron mobility transistor device as claimed in claim 1, further comprising another stress-relief layer disposed between every two pairs of alternating layers.

### Claim 5 (depends on 1)

The high electron mobility transistor device as claimed in claim 1, wherein a thickness of the stress-relief layer ranges from 0.1 nm to 10 nm.

### Claim 6 (depends on 1)

The high electron mobility transistor device as claimed in claim 1, wherein a thickness of the carbon-doped gallium nitride layer ranges from 1 nm to 600 nm, and a thickness of the undoped gallium nitride layer ranges from 1 nm to 200 nm.

### Claim 7 (depends on 1)

The high electron mobility transistor device as claimed in claim 1, wherein a ratio of a thickness of the carbon-doped gallium nitride layer to a thickness of the undoped gallium nitride layer ranges from 3.5 to 5.

### Claim 8 (depends on 1)

The high electron mobility transistor device as claimed in claim 1, further comprising a nucleation layer disposed between the substrate and the plurality of pairs of alternating layers.

### Claim 9 (depends on 8)

The high electron mobility transistor device as claimed in claim 8, wherein the nucleation layer comprises aluminum nitride (AlN), aluminum gallium nitride (AlGaN), or a combination thereof.

### Claim 10 (depends on 1)

The high electron mobility transistor device as claimed in claim 1, wherein the buffer layer comprises gallium nitride (GaN), aluminum nitride (AlN), aluminum gallium nitride (AlGaN), or a combination thereof.

### Claim 11 (depends on 1)

The high electron mobility transistor device as claimed in claim 1, further comprising:
a source, a drain, and a gate disposed over the barrier layer.

### Claim 12

A method for forming high electron mobility transistor devices, comprising:
forming a substrate;
forming a buffer layer over the substrate, wherein the buffer layer comprises a gradient buffer layer formed over a superlattice buffer layer, and wherein the superlattice buffer layer comprises a plurality of pairs of AlN layers and AlGaN layers, the gradient buffer layer comprises a plurality of AlGaN layers with different concentrations, and one of the plurality of AlGaN layers of the gradient buffer layer is in contact with one of the AlN layers of the superlattice buffer layer;
forming a plurality of pairs of alternating layers over the buffer layer, wherein each pair of alternating layers comprises a carbon-doped gallium nitride layer and an undoped gallium nitride layer, and a topmost layer of the pairs of alternating layers is a topmost undoped gallium nitride layer;
forming a stress-relief layer over the topmost undoped gallium nitride layer;
forming a gallium nitride layer over the stress-relief layer, wherein the stress-relief layer is in contact with the gallium nitride layer and the topmost undoped gallium nitride layer; and
forming a barrier layer disposed over the gallium nitride layer, wherein a 2DEG is created at the interface between the gallium nitride layer and the barrier layer.

### Claim 13 (depends on 12)

The method as claimed in claim 12, wherein the plurality of pairs of alternating layers comprises aluminum nitride, aluminum gallium nitride, or a combination thereof, and the stress-relief layer comprises aluminum nitride, aluminum gallium nitride, or a combination thereof.

### Claim 14 (depends on 12)

The method as claimed in claim 12, further comprising forming another stress-relief layer between every two pairs of alternating layers.

### Claim 15 (depends on 12)

The method as claimed in claim 12, wherein a thickness of the stress-relief layer ranges from 0.1 nm to 10 nm.

### Claim 16 (depends on 12)

The method as claimed in claim 12, wherein a thickness of the carbon-doped gallium nitride layer ranges from 1 nm to 600 nm, a thickness of the undoped gallium nitride layer ranges from 1 nm to 200 nm, and a ratio of the thickness of the carbon-doped gallium nitride layer to the thickness of the undoped gallium nitride layer ranges from 3.5 to 5.

### Claim 17 (depends on 12)

The method as claimed in claim 12, further comprising forming a nucleation layer between the substrate and the plurality of pairs of alternating layers, wherein the nucleation layer comprises aluminum nitride, aluminum gallium nitride, or a combination thereof.