Insulated gate turn-off device with designated breakdown areas between gate trenches

A vertical insulated gate turn-off (IGTO) device comprising:

• a first semiconductor layer of a first conductivity type;
• a second semiconductor layer of a second conductivity type overlying the first semiconductor layer;
• and
• an array of cells comprising:
• a plurality of first insulated gates within trenches in the second semiconductor layer, the first insulated gates being electrically connected together, the first insulated gates having a gate oxide layer along sidewalls of the trenches;
• and
• first regions of the second conductivity type within the second semiconductor layer between at least some of the trenches, the first regions having a dopant concentration higher than a dopant concentration in the second semiconductor layer,
• wherein a first portion of the second semiconductor layer is located above the first regions, and a second portion of the second semiconductor layer is located below the first regions,
• wherein the cells conduct a current when the first insulated gates are biased beyond a threshold voltage;
• wherein the first regions extend above and below a bottom of the trenches.

A method of forming a vertical insulated gate turn-off (IGTO) device comprising:

• providing a first semiconductor layer of a first conductivity type;
• forming a second semiconductor layer of a second conductivity type overlying the first semiconductor layer;
• etching trenches at least into the second semiconductor layer, the trenches having sidewalls;
• implanting dopants of the second conductivity type at an angle into the sidewalls of the trenches and into mesas of the second semiconductor layer between the trenches to form first regions of the second conductivity type within the second semiconductor layer between at least some of the trenches, the first regions having a dopant concentration higher than a dopant concentration in the second semiconductor layer, wherein the first regions do not extend to the trenches,
• forming a gate oxide layer on the sidewalls of the trenches;
• and
• depositing a conductive material into the trenches to form insulated gates,
• wherein the IGTO device conducts a current when the gates are biased beyond a threshold voltage.

A method of forming a vertical insulated gate turn-off (IGTO) device comprising:

• providing a first semiconductor layer of a first conductivity type;
• forming a second semiconductor layer of a second conductivity type overlying the first semiconductor layer;
• etching trenches at least into the second semiconductor layer, the trenches having sidewalls;
• forming a gate oxide layer on the sidewalls of the trenches;
• depositing a conductive material into the trenches to form insulated gates;
• forming a dielectric material over the gates and over edges of the trenches for forming spacers;
• and
• implanting dopants of the second conductivity type into mesas of the second semiconductor layer between the trenches, using the dielectric material as a mask, to form first regions of the second conductivity type within the second semiconductor layer between at least some of the trenches, the first regions having a dopant concentration higher than a dopant concentration in the second semiconductor layer, wherein a first portion of the second semiconductor layer is located above the first regions, and a second portion of the second semiconductor layer is located below the first regions, wherein the first regions do not extend to the trenches,
• wherein the IGTO device conducts a current when the gates are biased beyond a threshold voltage.

A method of forming a vertical insulated gate turn-off (IGTO) device comprising:

• providing a first semiconductor layer of a first conductivity type;
• forming a second semiconductor layer of a second conductivity type overlying the first semiconductor layer;
• etching trenches at least into the second semiconductor layer, the trenches having sidewalls;
• forming a gate oxide layer on the sidewalls of the trenches;
• depositing a conductive material into the trenches to form insulated gates;
• forming a dielectric material over the gates and over edges of the trenches for forming spacers;
• and
• implanting dopants of the second conductivity type into mesas of the second semiconductor layer between the trenches, using the dielectric material as a mask, to form first regions of the second conductivity type within the second semiconductor layer between at least some of the trenches, the first regions having a dopant concentration higher than a dopant concentration in the second semiconductor layer, wherein a first portion of the second semiconductor layer is located above the first regions, and a second portion of the second semiconductor layer is located below the first regions,
• wherein the IGTO device conducts a current when the gates are biased beyond a threshold voltage;
• wherein the first regions extend above and below a bottom of the trenches.