# US 11,114,547 B2 · Field effect transistor with negative capacitance dieletric structures

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- Number: US 11,114,547 B2
- Document ID: US11114547B2
- Status: Granted
- Kind: B2
- Application number: 16/573,334
- Filed: 2019-09-17
- Published: 2021-03-18
- Granted: 2021-09-07
- Earliest claimed: 2019-09-17
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Chansyun David Yang; Keh-Jeng Chang; Chan-Lon Yang
- Web page: https://patentgrep.com/patent/US11114547B2

## CPC

- H10D 64/018: {Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/0196: {by modifying properties of the inner spacers}
- H10D 30/0243: {using dummy structures having essentially the same shapes as the semiconductor bodies, e.g. to provide stability}
- H10D 30/508: {characterised by the relative sizes, shapes or dispositions of the inner spacers}
- H10D 30/509: {characterised by the material of the inner spacers}
- H10D 30/6212: {having fin-shaped semiconductor bodies having non-rectangular cross-sections}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6739: {Conductor-insulator-semiconductor electrodes}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 62/121: {oriented parallel to substrates}
- H10D 64/015: {removing at least parts of gate spacers, e.g. disposable spacers}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 64/118: {Electrodes comprising insulating layers having particular dielectric or electrostatic properties, e.g. having static charges}
- H10D 64/685: {being perpendicular to the channel plane}
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10D 62/364: {of IGFETs}
- H10P 14/6339: {deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD}
- H10P 14/69392: {the material containing hafnium, e.g. HfO2}
- H10P 50/242: {of Group IV materials}
- H10P 50/283: {by chemical means}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

The structure of a semiconductor device with negative capacitance (NC) dielectric structures and a method of fabricating the semiconductor device are disclosed. A method of fabricating the semiconductor device includes forming a fin structure with a fin base portion and a fin top portion on a substrate, forming a spacer structure in a first region of the fin top portion, and forming a gate structure on a second region of the fin top portion. The spacer structure includes a first NC dielectric material and the gate structure includes a gate dielectric layer with a second NC dielectric material different from the first NC dielectric material.

## Claims

### Claim 1

A method of fabricating a semiconductor device, the method comprising:
forming a fin structure with a fin base portion and a fin top portion on a substrate;
forming a spacer structure in a first region of the fin top portion, wherein the spacer structure comprises a first negative capacitance (NC) dielectric layer comprising an NC dielectric material, a non-NC dielectric structure and an air gap within the first NC dielectric layer; and
forming a gate structure on a second region of the fin top portion,
wherein the gate structure comprises a gate dielectric layer with a second NC dielectric material different from the first NC dielectric material.

### Claim 2 (depends on 1)

The method of claim 1, wherein the forming the spacer structure comprises:
forming a recessed region in the first region of the fin top portion; and
depositing a layer of the first NC dielectric material in the recessed region.

### Claim 3 (depends on 2)

The method of claim 2, wherein the depositing the layer of the first NC dielectric material comprises:
depositing a layer of high-k dielectric material;
doping the layer of high-k dielectric material with a conductive material.

### Claim 4 (depends on 1)

The method of claim 1, wherein the forming the spacer structure comprises:
forming a recessed region in the first region of the fin top portion;
depositing a layer of the first NC dielectric material to line sides of the recessed region; and
forming the non-NC dielectric structure and the air gap on the layer of the first NC dielectric material within the recessed region.

### Claim 5 (depends on 4)

The method of claim 4, wherein the forming the non-NC dielectric structure and the air gap comprises:
depositing a layer of non-NC dielectric material to substantially fill an area of the recessed region lined with the layer of the first NC dielectric material;
etching back the layer of non-NC dielectric material; and
epitaxially growing a source/drain region on the fin base portion and the first region of the fin top portion, wherein the source/drain region covers an opening of the recessed region and forms the air gap between the source/drain region and the etched backed layer of non-NC dielectric material.

### Claim 6 (depends on 1)

The method of claim 1, wherein the forming the gate structure comprises etching a fin portion in the second region of the fin top portion, and
wherein the fin portion is adjacent to the spacer structure.

### Claim 7 (depends on 1)

The method of claim 1, wherein the forming the gate structure comprises depositing a layer of the second NC dielectric layer on the second region of the fin top portion, and
wherein the second region is adjacent to the spacer structure.

### Claim 8 (depends on 7)

The method of claim 7, wherein the depositing the layer of the second NC dielectric layer comprises:
depositing a layer of hafnium oxide; and
doping the layer of hafnium oxide with a metal.

### Claim 9 (depends on 1)

The method of claim 1, wherein the forming the gate structure comprises depositing the layer of the second NC dielectric layer wrapped around the second region of the fin top portion.

### Claim 10 (depends on 1)

The method of claim 1, wherein the forming the gate structure comprises depositing a work function metal layer wrapped around the second region of the fin top portion.

### Claim 11

A method of fabricating a semiconductor device, the method comprising:
forming a fin structure with a stacked fin portion and a fin base portion on a substrate, wherein the stacked fin portion is epitaxially grown on the fin base portion;
forming an epitaxial source/drain region on the fin structure;
forming a first negative capacitance (NC) dielectric structure in a first region of the stacked fin portion, wherein the first NC dielectric structure comprises a first dielectric layer with a first NC material;
forming gate structures on a second region of the stacked fin portion, wherein the gate structures each comprises a second dielectric layer with the first NC material;
forming a source/drain contact structure on the epitaxial source/drain region; and
forming a second NC dielectric structure between the source/drain contact structure and the gate structures, wherein the second NC dielectric structure comprises a third dielectric layer with the first NC material.

### Claim 12 (depends on 11)

The method of claim 11, wherein the forming the first NC dielectric structure comprises:
forming a recessed region in the first region of the stacked fin portion;
depositing a layer of the first NC material within the recessed region; and
forming a dielectric structure on the layer of the first NC material within the recessed region.

### Claim 13 (depends on 11)

The method of claim 11, wherein the forming the second NC dielectric structure comprises:
forming a trench on the epitaxial source/drain region between the gate structures;
depositing a layer of the first NC material along sides of the trench;
depositing a nitride layer on the layer of the first NC material; and
etching back the nitride layer.

### Claim 14 (depends on 13)

The method of claim 13, wherein the depositing the layer of the first NC material comprises:
depositing a layer of high-k dielectric material; and
doping the layer of high-k dielectric material with a conductive material.

### Claim 15 (depends on 13)

The method of claim 13, wherein the depositing the layer of the first NC material comprises:
depositing a layer of hafnium oxide;
doping the layer of hafnium oxide with a metal; and
annealing the doped hafnium oxide.

### Claim 16

A method of fabricating a semiconductor device, the method comprising:
forming a fin structure with a fin base portion and a fin top portion on a substrate;
forming a spacer structure in a first region of the fin top portion, wherein the spacer structure comprises a negative capacitance (NC) dielectric layer comprising an NC dielectric material, a non-NC dielectric structure, and an air gap;
forming a source/drain region on the fin base portion and in contact with the fin top portion, wherein the source/drain region, the NC dielectric layer, and the non-NC dielectric structure enclose the air gap; and
forming a gate structure on a second region of the fin top portion, wherein the gate structure comprises a gate dielectric layer having the NC dielectric material.

### Claim 17 (depends on 16)

The method of claim 16, wherein the forming the spacer structure comprises:
forming a recessed region in the first region of the fin top portion;
depositing a layer of the NC dielectric material in the recessed region;
depositing a layer of non-NC dielectric material to substantially fill the recessed region;
etching back the layer of non-NC dielectric material to form the non-NC dielectric structure; and
etching back the layer of NC dielectric material to form the NC dielectric layer.

### Claim 18 (depends on 17)

The method of claim 17, wherein the depositing the layer of the NC dielectric material comprises:
depositing a layer of high-k dielectric material; and
doping the layer of high-k dielectric material with a conductive material.

### Claim 19 (depends on 17)

The method of claim 17, wherein the depositing the layer of the NC material comprises:
depositing a layer of hafnium oxide;
doping the layer of hafnium oxide with a metal; and
annealing the doped layer of hafnium oxide.

### Claim 20 (depends on 16)

The method of claim 16, wherein the forming the gate structure comprises:
etching a fin portion in the second region of the fin top portion, wherein the fin portion is adjacent to the spacer structure;
depositing a layer of the NC dielectric material wrapped around the second region of the fin top portion; and
depositing a work function metal layer on the gate dielectric layer.