# US 11,114,544 B2 · Integrated circuit device having fin-type active

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- Number: US 11,114,544 B2
- Document ID: US11114544B2
- Status: Granted
- Kind: B2
- Application number: 16/552,150
- Filed: 2019-08-27
- Published: 2020-05-28
- Granted: 2021-09-07
- Earliest claimed: 2018-11-23
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Dae-young Kwak; Ji-ye Kim; Jung-hwan Chun; Min-chan Gwak; Dong-hyun Roh; Jin-wook Lee; Sang-jin Hyun
- Web page: https://patentgrep.com/patent/US11114544B2

## CPC

- H10D 30/0215: {using self-aligned selective metal deposition simultaneously on gate electrodes and the source regions or drain regions}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10B 10/12: {comprising a MOSFET load element}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10D 84/0186: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/83125: {the IGFETs characterised by having shared source or drain regions}
- H10D 84/853: {comprising FinFETs}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/0693: {by forming self-aligned vias}
- H10W 20/075: {of multilayered thin functional dielectric layers}
- H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)}
- H10W 20/082: {the openings being tapered via holes}
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W 20/076: {in via holes or trenches}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

An integrated circuit device includes a fin-type active region protruding from a top surface of a substrate and extending in a first direction parallel to the top surface of the substrate, a gate structure intersecting with the fin-type active region and extending on the substrate in a second direction perpendicular to the first direction, a source/drain region on a first side of the gate structure, a first contact structure on the source/drain region, and a contact capping layer on the first contact structure. A top surface of the first contact structure has a first width in the first direction, a bottom surface of the contact capping layer has a second width greater than the first width stated above in the first direction, and the contact capping layer includes a protruding portion extending outward from a sidewall of the first contact structure.

## Claims

### Claim 1

An integrated circuit device comprising:
a fin-type active region protruding from a top surface of a substrate and extending in a first direction that is parallel to the top surface of the substrate;
a gate structure on a top surface of the fin-type active region and extending on the substrate in a second direction that is perpendicular to the first direction;
a source/drain region on a first side of the gate structure and adjacent a side surface of the fin-type active region that protrudes from the top surface of the substrate;
a first contact structure on the source/drain region;
a contact capping layer on the first contact structure; and
a second contact structure on the gate structure,
wherein a top surface of the first contact structure has a first width in the first direction,
wherein a bottom surface of the contact capping layer has a second width that is greater than the first width of the top surface of the first contact structure in the first direction, and
wherein the contact capping layer comprises a protruding portion extending outward from a sidewall of the first contact structure, and
wherein a portion of a sidewall of the second contact structure is around the contact capping layer.

### Claim 2 (depends on 1)

The integrated circuit device according to claim 1, wherein a sidewall of the contact capping layer protrudes outwards from the sidewall of the first contact structure in the first direction and the second direction.

### Claim 3 (depends on 1)

The integrated circuit device according to claim 1, wherein a first width of the second contact structure at a same first height as the bottom surface of the contact capping layer relative to the substrate is less than a second width of the second contact structure at a same second height as a top surface of the contact capping layer relative to the substrate.

### Claim 4 (depends on 1)

The integrated circuit device according to claim 1, further comprising:
an interlayer dielectric on the gate structure and the source/drain region,
wherein the contact capping layer and an upper portion of the first contact structure are in a first contact hole which penetrates the interlayer dielectric, and
wherein a sidewall of the contact capping layer is exposed at an inner wall of a second contact hole.

### Claim 5 (depends on 1)

The integrated circuit device according to claim 1, further comprising:
an interlayer dielectric on the gate structure and the source/drain region,
wherein an upper portion of the first contact structure and the contact capping layer are in a first contact hole which penetrates the interlayer dielectric,
wherein the first contact hole comprises an enlarged upper region, and
wherein the contact capping layer is in the enlarged upper region.

### Claim 6 (depends on 5)

The integrated circuit device according to claim 5,
wherein the contact capping layer comprises a first capping layer filling the enlarged upper region,
wherein a bottom surface of the first capping layer contacts the top surface of the first contact structure, and
wherein a top surface of the first capping layer is at a same height as a top surface of the interlayer dielectric relative to the substrate.

### Claim 7 (depends on 5)

The integrated circuit device according to claim 5, wherein the contact capping layer comprises:
a first capping layer conformally arranged on an inner wall of the enlarged upper region; and
a second capping layer on the first capping layer in the enlarged upper region.

### Claim 8 (depends on 7)

The integrated circuit device according to claim 7,
wherein the first capping layer comprises silicon carbide comprising carbon in a first amount, and
wherein the second capping layer comprises silicon carbide comprising carbon in a second amount that is lower than the first amount.

### Claim 9 (depends on 5)

The integrated circuit device according to claim 5,
wherein the contact capping layer comprises a second capping layer and a first capping layer, which are sequentially arranged on the first contact structure in the enlarged upper region, and
wherein a top surface of the first capping layer is coplanar with a top surface of the interlayer dielectric.

### Claim 10

An integrated circuit device comprising:
first and second fin-type active regions protruding from a top surface of a substrate and extending in a first direction that is parallel to the top surface of the substrate;
first and second gate structures extending on the substrate in a second direction that is perpendicular to the first direction;
a first source/drain region on a first side of the first gate structure, wherein the first gate structure partially overlaps the first source/drain region in a direction perpendicular to the substrate;
a first contact structure on the first source/drain region;
a contact capping layer on the first contact structure, the contact capping layer including a protruding portion extending outward from a sidewall of the first contact structure; and
an interlayer dielectric on the first and second gate structures and the first source/drain region,
wherein the contact capping layer comprises a first capping layer and a second capping layer, which are sequentially arranged on the first contact structure,
wherein the first capping layer is arranged on the first contact structure and a sidewall of a first contact hole which penetrates the interlayer dielectric,
wherein the first capping layer is on a sidewall and a bottom surface of the second capping layer, and
wherein the second capping layer is not in contact with the interlayer dielectric.

### Claim 11 (depends on 10)

The integrated circuit device according to claim 10, further comprising:
a second source/drain region on a second side of the first gate structure, the second side being opposite to the first side; and
a second contact structure on the second source/drain region, the second contact structure including a first portion and a second portion, the second portion vertically overlapping the second source/drain region.

### Claim 12 (depends on 10)

The integrated circuit device according to claim 10, wherein an upper portion of the first contact structure has a first width that is greater than a second width of a bottom portion of the first contact structure.

### Claim 13 (depends on 10)

The integrated circuit device according to claim 10, wherein an upper portion of the first contact structure has a first width in the first direction that is less than a third width of a bottom portion of the contact capping layer in the first direction.

### Claim 14

An integrated circuit device comprising:
a fin-type active region protruding from a top surface of a substrate and extending in a first direction that is parallel to the top surface of the substrate;
a gate structure intersecting with the fin-type active region and extending on the substrate in a second direction that is perpendicular to the first direction;
a source/drain region on a first side of the gate structure;
an interlayer dielectric on the gate structure and the source/drain region;
a first contact structure in a lower portion of a contact hole and connected to the source/drain region, the contact hole penetrating the interlayer dielectric; and
a contact capping layer in an upper portion of the contact hole and on the first contact structure,
wherein the contact capping layer comprises a protruding portion extending outward from a sidewall of the first contact structure, and
wherein the protruding portion is at least partially surrounded by the interlayer dielectric.

### Claim 15 (depends on 14)

The integrated circuit device according to claim 14,
wherein the gate structure includes a gate line extending in the second direction and a gate spacer on a sidewall of the gate line, and
wherein the protruding portion vertically overlaps the gate spacer of the gate structure.

### Claim 16 (depends on 14)

The integrated circuit device according to claim 14, further comprising:
a second contact structure connected to the gate structure through the interlayer dielectric,
wherein a portion of a sidewall of the second contact structure is at least partially surrounded by the contact capping layer, and
wherein a first width of the second contact structure at a same first height as a bottom surface of the contact capping layer relative to the substrate is less than a second width of the second contact structure at a same second height as a top surface of the contact capping layer relative to the substrate.

### Claim 17 (depends on 16)

The integrated circuit device according to claim 16,
wherein the contact capping layer comprises a first capping layer and a second capping layer, which are sequentially arranged on the first contact structure,
wherein a sidewall and a bottom surface of the first capping layer form the protruding portion of the contact capping layer, and
wherein a lowermost surface of the first capping layer is at a lower third height than a fourth height of the protruding portion relative to the substrate.

### Claim 18 (depends on 16)

The integrated circuit device according to claim 16, wherein a top surface of the second contact structure is at a same fifth height as the top surface of the contact capping layer relative to the substrate.