# US 11,114,540 B2 · Semiconductor device including standard cells with header/footer switch including negative capacitance

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- Number: US 11,114,540 B2
- Document ID: US11114540B2
- Status: Granted
- Kind: B2
- Application number: 16/585,515
- Filed: 2019-11-04
- Published: 2020-02-13
- Granted: 2021-09-07
- Earliest claimed: 2017-09-18
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Chien-Hsing Lee; Chih-Sheng Chang; Wilman Tsai; Chia-Wen Chang; Ling-Yen Yeh; Carlos H. Diaz
- Web page: https://patentgrep.com/patent/US11114540B2

## CPC

- H10D 64/689: {having ferroelectric layers}
- H10B 10/12: {comprising a MOSFET load element}
- H10D 30/0415: {of FETs having ferroelectric gate insulators}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D 64/01: Manufacture or treatment
- H10D 64/033: {comprising ferroelectric layers}
- H10D 64/035: {comprising conductor-insulator-conductor-insulator-semiconductor structures}
- H10D 64/647: {Schottky drain or source electrodes for IGFETs}
- H10D 64/681: {having a compositional variation, e.g. multilayered}
- H10D 84/811: {Combinations of field-effect devices and one or more diodes, capacitors or resistors}
- H10D 84/853: {comprising FinFETs}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A semiconductor device includes a first potential supply line for supplying a first potential, a second potential supply line for supplying a second potential lower than the first potential, a functional circuit, and at least one of a first switch disposed between the first potential supply line and the functional circuit and a second switch disposed between the second potential supply line and the functional circuit. The first switch and the second switch are negative capacitance FET.

## Claims

### Claim 1

A semiconductor device, comprising:
a first potential supply line for supplying a first potential;
a second potential supply line for supplying a second potential lower than the first potential;
a functional circuit including a PMOS transistor and a NMOS transistor; and
a switch disposed between the first potential supply line and one of the PMOS transistor and the NMOS transistor of the functional circuit, wherein:
a voltage potential of the first potential supply line is supplied to the functional circuit via the switch,
the switch includes a negative capacitance (NC) MOS FET showing a negative capacitance, and a drain or a source of the NC MOS FET is directly connected to the first potential supply line without interposing any electronic devices,
the NMOS and PMOS transistors are normal MOS FETs, where in an NC MOS FET, a gate voltage is applied to a gate dielectric layer through a negative capacitor, and in a normal MOS FET, a gate voltage is applied to a gate dielectric layer without a negative capacitor,
a gate dielectric layer of the NC MOS FET includes a first dielectric layer and a second dielectric layer disposed on and in direct contact with the first dielectric layer, and
the second dielectric layer includes a ferroelectric material.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein:
the NC MOS FET includes a gate electrode disposed over the second dielectric layer of the gate dielectric layer, and
the gate dielectric layer has a U-shape cross section and a top of the gate dielectric layer is covered by and in direct contact with the gate electrode.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein the ferroelectric material is one or more selected from the group consisting of ZrO2, ZrAlSiO, HfO2, ZrO2 doped with Si, ZrO2 doped with Al HfZrO2, HfO2 doped with Zr (HfZrOx), HfO2 doped with Al (HfAlOx), and HfO2 doped with Si (HfSiOx).

### Claim 4 (depends on 3)

The semiconductor device of claim 3, wherein a thickness of the second dielectric layer is in a range from 1.0 nm to 10 nm.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the functional circuit includes a static random access memory.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the switch is disposed between the first potential supply line and the PMOS transistor.

### Claim 7 (depends on 6)

The semiconductor device of claim 6, wherein:
the functional circuit includes an internal potential supply line to which a source of the PMOS transistor is coupled, and
the drain of the NC MOS FET of the switch is coupled to the internal potential supply line and the source of the NC MOS FET of the switch is coupled to the first potential supply line.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein the switch is disposed between the first potential supply line and the NMOS transistor.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, wherein:
the functional circuit includes an internal potential supply line to which a drain of the NMOS transistor is coupled, and
the source of the NC MOS FET of the switch is coupled to the internal potential supply line and the drain of the NC MOS FET of the switch is coupled to the first potential supply line.

### Claim 10

A semiconductor device, comprising:
a first potential supply line for supplying a first potential;
a second potential supply line for supplying a second potential lower than the first potential;
a functional circuit including a CMOS circuit constituted by normal MOS FETs; and
a switch disposed between the first potential supply line and the CMOS circuit of the functional circuit, wherein:
a voltage potential of the first potential supply line is supplied to the CMOS circuit via the switch, and
the switch consists of a negative capacitance (NC) MOS FET,
in an NC MOS FET, a gate voltage is applied to a gate dielectric layer through a negative capacitor, and in a normal MOS FET, a gate voltage is applied to a gate dielectric layer without a negative capacitor,
a gate dielectric layer of the NCFET includes a first dielectric layer and a second dielectric layer disposed on and in direct contact with the first dielectric layer, a gate electrode disposed on and in direct contact with the first dielectric layer and the second dielectric layer,
the second dielectric layer includes a ferroelectric material, and
a top of the first and second gate dielectric layers is below a top of the gate electrode.

### Claim 11 (depends on 10)

The semiconductor device of claim 10, wherein the CMOS circuit is an inverter.

### Claim 12 (depends on 10)

The semiconductor device of claim 10, wherein the ferroelectric material is one or more selected from the group consisting of ZrO2, ZrAlSiO, ZrO2 doped with Si, ZrO2 doped with Al HfO2, HfZrO2, HfO2 doped with Zr (HfZrOx), HfO2 doped with Al (HfAlOx), and HfO2 doped with Si (HfSiOx).

### Claim 13 (depends on 12)

The semiconductor device of claim 12, wherein a thickness of the second dielectric layer is in a range from 1.0 nm to 10 nm.

### Claim 14 (depends on 10)

The semiconductor device of claim 10, wherein:
the functional circuit includes a first internal potential supply line and a second internal potential supply line, and
the CMOS circuit is disposed between and coupled to the first and second potential supply lines.

### Claim 15

A semiconductor device, comprising:
a first potential supply line for supplying a first potential;
a first internal potential supply line and a second internal potential supply line separated from the first internal potential supply line, both for supplying the first potential;
a second potential supply line for supplying a second potential lower than the first potential;
a first functional circuit including a PMOS transistor and a NMOS transistor;
a second functional circuit including a PMOS transistor and a NMOS transistor;
a first negative capacitance (NC) FET disposed between the first potential supply line and the first internal potential supply line; and
a second NC FET disposed between the first potential supply line and the second internal potential supply line, wherein:
the NMOS and PMOS transistors are normal MOS FETs,
in an NC MOS FET, a gate voltage is applied to a gate dielectric layer through a negative capacitor, and in a normal MOS FET, a gate voltage is applied to a gate dielectric layer without a negative capacitor,
each of the first and second NC FETs includes a first dielectric layer and a second dielectric layer disposed over the first dielectric layer, a gate electrode disposed over the second dielectric layer,
the second dielectric layer includes a ferroelectric material, and
a top of the first and second gate dielectric layers is below a top of the gate electrode.

### Claim 16 (depends on 15)

The semiconductor device of claim 15, wherein the functional circuit includes a CMOS inverter constituted by normal MOS FETs.

### Claim 17 (depends on 15)

The semiconductor device of claim 15, wherein the ferroelectric material is one or more selected from the group consisting of ZrO2, ZrAlSiO, HfO2, HfZrO2, HfO2 doped with Zr (HfZrOx), HfO2 doped with Al (HfAlOx), and HfO2 doped with Si (HfSiOx).

### Claim 18 (depends on 17)

The semiconductor device of claim 17, wherein a thickness of the second dielectric layer is in a range from 1.0 nm to 10 nm.

### Claim 19 (depends on 15)

The semiconductor device of claim 15, wherein the functional circuit includes a static random access memory.

### Claim 20 (depends on 15)

The semiconductor device of claim 15, further comprising:
a third internal potential supply line and a fourth internal potential supply line separated from the third internal potential supply line, both for supplying the second potential;
a third NC FET disposed between the second potential supply line and the third internal potential supply line; and
a fourth NC FET disposed between the second potential supply line and the fourth internal potential supply line.