# US 11,114,539 B2 · Gate stack for heterostructure device

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- Number: US 11,114,539 B2
- Document ID: US11114539B2
- Status: Granted
- Kind: B2
- Application number: 16/158,560
- Filed: 2018-10-12
- Published: 2019-04-18
- Granted: 2021-09-07
- Earliest claimed: 2017-10-12
- Assignees: Power Integrations, Inc.
- Applicants: Power Integrations, Inc.
- Inventors: Jamal Ramdani
- Web page: https://patentgrep.com/patent/US11114539B2

## CPC

- H10D 64/685: {being perpendicular to the channel plane}
- H10D 30/015: {of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT}
- H10D 30/475: {having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs}
- H10D 30/4755: {having wide bandgap charge-carrier supplying layers, e.g. modulation doped HEMTs such as n-AlGaAs/GaAs HEMTs}
- H10D 62/824: comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions
- H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN}
- H10D 64/01358: {the insulator being formed after the semiconductor body, the semiconductor being a Group III-V material}
- H10D 64/111: {Field plates}
- H10D 64/514: {characterised by the insulating layers}
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10D 64/693: {the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials}
- H10P 14/6334: {using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition (deposition by physical ablation of a target H10P14/6329)}
- H10P 14/6905: {being a silicon carbide or silicon carbonitride and not containing oxygen, e.g. SiC or SiC:H}
- H10P 14/69391: {the material containing aluminium, e.g. Al2O3}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A heterostructure semiconductor device includes a first active layer and a second active layer disposed on the first active layer. A two-dimensional electron gas layer is formed between the first and second active layers. A sandwich gate dielectric layer structure is disposed on the second active layer. A passivation layer is disposed over the sandwich gate dielectric layer structure. A gate extends through the passivation layer to the sandwich gate dielectric layer structure. First and second ohmic contacts electrically connected to the second active layer. The first and second ohmic contacts are laterally spaced-apart, with the gate being disposed between the first and second ohmic contacts.

## Claims

### Claim 1

A heterostructure semiconductor device comprising:
a first active layer;
a second active layer disposed on the first active layer, a two-dimensional electron gas layer formed between the first and second active layers;
a sandwich gate dielectric layer structure disposed on the second active layer, wherein at least one layer of the sandwich gate dielectric layer structure is an ex-situ deposited layer formed through atomic layer deposition (ALD) with O2 plasma as compared to the first active layer and the second active layer and at least another layer of the sandwich gate dielectric layer structure is an in-situ deposited layer formed through metal-organic chemical vapor deposition (MOCVD) as compared to the first active layer and the second active layer, wherein the in-situ deposited layer has a thickness between 30-60 nanometers such that a critical voltage of the heterostructure semiconductor device is between approximately 100-170 volts;
a passivation layer disposed over the sandwich gate dielectric layer structure;
a gate that extends through the passivation layer to the top of the sandwich gate dielectric layer structure, wherein the gate is vertically separated from the second active layer by the sandwich gate dielectric layer structure and the sandwich gate dielectric layer structure is beneath a bottommost surface of the gate; and
first and second ohmic contacts disposed on the second active layer, the first and second ohmic contacts being laterally spaced-apart, the gate being disposed between the first and second ohmic contacts, wherein the two-dimensional electron gas layer is formed between the first and second active layers beneath the first and second ohmic contacts and the gate, wherein the heterostructure semiconductor device is a high-voltage FET.

### Claim 2 (depends on 1)

The heterostructure semiconductor device of claim 1 wherein the sandwich gate dielectric layer structure comprises:
a first gate dielectric layer disposed on the second active layer;
a second gate dielectric layer disposed on the first gate dielectric layer; and
a third gate dielectric layer disposed on the second gate dielectric layer.

### Claim 3 (depends on 2)

The heterostructure semiconductor device of claim 2 wherein the third gate dielectric layer comprises aluminum oxide (Al2O3).

### Claim 4 (depends on 2)

The heterostructure semiconductor device of claim 2 wherein the first gate dielectric layer has a first thickness; the second gate dielectric layer has a second thickness, the third gate dielectric layer has a third thickness, and the second thickness is larger than the first thickness and the third thickness.

### Claim 5 (depends on 2)

The heterostructure semiconductor device of claim 2 wherein the first gate dielectric layer comprises a nitride-based compound.

### Claim 6 (depends on 2)

The heterostructure semiconductor device of claim 2 wherein the first gate dielectric layer comprises silicon nitride (SiN).

### Claim 7 (depends on 2)

The heterostructure semiconductor device of claim 2 wherein the first gate dielectric layer comprises carbon nitride (CN).

### Claim 8 (depends on 2)

The heterostructure semiconductor device of claim 2 wherein the first gate dielectric layer comprises boron nitride (BN).

### Claim 9 (depends on 2)

The heterostructure semiconductor device of claim 2, wherein the first gate dielectric layer and the second gate dielectric layer comprise the same material.

### Claim 10 (depends on 2)

The heterostructure semiconductor device of claim 2, wherein the first gate dielectric layer and the second gate dielectric are in-situ deposited layers with the first active layer and the second active layer formed through metal-organic chemical vapor deposition (MOCVD), and the third gate dielectric layer is an ex-situ deposited layer as compared to the first active layer and the second active layer.

### Claim 11 (depends on 2)

The heterostructure semiconductor device of claim 2 wherein the first gate dielectric layer has a first thickness in a range of approximately 1-5 nanometers;
the second gate dielectric layer has a second thickness in a range of approximately 20-60 nanometers; and the third gate dielectric has a third thickness in a range of 10-20 nanometers.

### Claim 12 (depends on 11)

The heterostructure semiconductor device of claim 11 wherein the first, second, and third thicknesses are set such that a leakage current through the gate is substantially constant versus temperature during normal operation of the heterostructure semiconductor device.

### Claim 13 (depends on 11)

The heterostructure semiconductor device of claim 11 wherein the first, second, and third thicknesses are set such that a threshold voltage is substantially constant versus temperature during normal operation of the heterostructure semiconductor device.

### Claim 14 (depends on 11)

The heterostructure semiconductor device of claim 11 wherein a sum of the first thickness of the first gate dielectric layer and the second thickness of the second gate dielectric layer is approximately 30-60 nanometers.

### Claim 15 (depends on 1)

The heterostructure semiconductor device according to claim 1 wherein the first active layer comprises gallium nitride (GaN) and the second active layer comprises aluminum gallium nitride (AlGaN).

### Claim 16 (depends on 1)

The heterostructure semiconductor device of claim 1 wherein the gate includes a gate field plate that extends toward the second ohmic contact, wherein the second ohmic contact is a drain contact.

### Claim 17 (depends on 1)

The heterostructure semiconductor device of claim 1 wherein the passivation layer comprises silicon nitride (SiN).