# US 11,114,538 B2 · Transistor with an airgap spacer adjacent to a transistor gate

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- Number: US 11,114,538 B2
- Document ID: US11114538B2
- Status: Granted
- Kind: B2
- Application number: 16/230,454
- Filed: 2018-12-21
- Published: 2019-04-25
- Granted: 2021-09-07
- Earliest claimed: 2018-12-21
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Chen-Guan Lee; Joodong Park; En-Shao Liu; Everett S. Cassidy-Comfort; Walid M. Hafez; Chia-Hong Jan
- Web page: https://patentgrep.com/patent/US11114538B2

## CPC

- H10D 64/679: {comprising air gaps}
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10W 10/021: {of air gaps}
- H10W 10/20: Air gaps
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/072: {of dielectric parts comprising air gaps}
- H10W 20/46: comprising air gaps
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A microelectronic transistor may be fabricated having an airgap spacer formed as a gate sidewall spacer, such that the airgap spacer is positioned between a gate electrode and a source contact and/or a drain contact of the microelectronic transistor. As the dielectric constant of gaseous substances is significantly lower than that of a solid or a semi-solid dielectric material, the airgap spacer may result in minimal capacitive coupling between the gate electrode and the source contact and/or the drain contact, which may reduce circuit delay of the microelectronic transistor.

## Claims

### Claim 1

A microelectronic transistor, comprising:
a microelectronic substrate;
a source region and a drain region formed in the microelectronic substrate;
a single layer of interlayer dielectric disposed over the microelectronic substrate;
a source contact extending through the interlayer dielectric and electrically contacting the source region;
a drain contact extending through the interlayer dielectric and electrically contacting the drain region;
a gate positioned between the source contact and the drain contact, wherein the gate comprises a gate dielectric layer and a gate electrode; and
an airgap spacer positioned between the gate and at least one of the source contact and the drain contact, wherein the airgap spacer is defined by only an exposed portion of the microelectronic substrate, an exposed portion of the single layer of interlayer dielectric, and an exposed portion of the gate, wherein the single layer of interlayer dielectric contacts the gate dielectric layer of the gate.

### Claim 2 (depends on 1)

The microelectronic transistor of claim 1, wherein the airgap spacer comprises a void having a gas disposed therein.

### Claim 3 (depends on 2)

The microelectronic transistor of claim 2, wherein the gas comprises air.

### Claim 4 (depends on 1)

The microelectronic transistor of claim 1, wherein the gate comprises the gate electrode, the gate dielectric layer, and a hard mask and wherein the exposed portion of the gate defining the airgap spacer comprises an exposed portion of the gate dielectric layer, and an exposed portion of the hard mask.

### Claim 5 (depends on 1)

The microelectronic transistor of claim 1, wherein the gate dielectric layer comprises a conformal layer abutting the gate electrode, and wherein the exposed portion of the gate defining the airgap spacer is only an exposed portion of the gate dielectric layer.

### Claim 6

A microelectronic transistor, comprising:
a microelectronic substrate;
a source region and a drain region formed in the microelectronic substrate;
a single layer of interlayer dielectric disposed over the microelectronic substrate;
a source contact extending through the interlayer dielectric and electrically contacting the source region;
a drain contact extending through the interlayer dielectric and electrically contacting the drain region;
a gate positioned between the source contact and the drain contact, wherein the gate comprises a gate dielectric layer and a gate electrode;
a gate hard mask, wherein the gate extends through the gate hard mask; and
an airgap spacer positioned between the gate and at least one of the source contact and the drain contact, wherein the airgap spacer is defined by only an exposed portion of the microelectronic substrate, an exposed portion of the gate, an exposed portion of the gate hard mask, and an exposed portion of the single layer of interlayer dielectric, wherein the single layer of interlayer dielectric contacts the gate dielectric layer of the gate.

### Claim 7 (depends on 6)

The microelectronic transistor of claim 6, wherein the airgap spacer comprises a void having a gas disposed therein.

### Claim 8 (depends on 7)

The microelectronic transistor of claim 7, wherein the gas comprises air.

### Claim 9 (depends on 6)

The microelectronic transistor of claim 6, wherein the gate dielectric layer is disposed between the gate electrode and the microelectronic substrate.

### Claim 10 (depends on 6)

The microelectronic transistor of claim 6, wherein the gate dielectric layer comprises a conformal layer abutting the gate electrode, and wherein the exposed portion of the gate defining the airgap spacer is only an exposed portion of the gate dielectric layer.

### Claim 11

An electronic system, comprising:
a board; and
a microelectronic component attached to the board, wherein the microelectronic component includes a microelectronic transistor comprising:
a microelectronic substrate;
a source region and a drain region formed in the microelectronic substrate;
a single layer of interlayer dielectric disposed over the microelectronic substrate;
a source contact extending through the interlayer dielectric and electrically contacting the source region;
a drain contact extending through the interlayer dielectric and electrically contacting the drain region;
a gate positioned between the source contact and the drain contact, wherein the gate comprises a gate dielectric layer and a gate electrode; and
an airgap spacer positioned between the gate and at least one of the source contact and the drain contact, wherein the airgap spacer is defined by only an exposed portion of the microelectronic substrate, an exposed portion of the single layer of interlayer dielectric, and an exposed portion of the gate, wherein the single layer of interlayer dielectric contacts the gate dielectric layer of the gate.

### Claim 12 (depends on 11)

The electronic system of claim 11, wherein the airgap spacer comprises a void having a gas disposed therein.

### Claim 13 (depends on 12)

The electronic system of claim 12, wherein the gas comprises air.

### Claim 14 (depends on 11)

The electronic system of claim 11, wherein the gate comprises the gate electrode, the gate dielectric layer, and a hard mask, and wherein the exposed portion of the gate defining the airgap spacer comprises an exposed portion of the gate dielectric layer and an exposed portion of the hard mask.

### Claim 15 (depends on 11)

The electronic system of claim 11, wherein the gate dielectric layer comprises a conformal layer abutting the gate electrode, and wherein the exposed portion of the gate defining the airgap spacer is only an exposed portion of the gate dielectric layer.

### Claim 16

An electronic system, comprising:
a board; and
a microelectronic component attached to the board, wherein the microelectronic component includes a microelectronic transistor comprising:
a microelectronic substrate;
a source region and a drain region formed in the microelectronic substrate;
a signal layer of interlayer dielectric disposed over the microelectronic substrate;
a source contact extending through the interlayer dielectric and electrically contacting the source region;
a drain contact extending through the interlayer dielectric and electrically contacting the source region;
a gate positioned between the source contact and the drain contact, wherein the gate comprises a gate dielectric layer and a gate electrode; and
a gate hard mask, wherein the gate extends through the gate hard mask; and
an airgap spacer positioned between the gate electrode and at least one of the source contact and the drain contact, wherein the airgap spacer is defined by only an exposed portion of the microelectronic substrate, an exposed portion of the gate, an exposed portion of the gate hard mask, and an exposed portion of the single layer of interlayer dielectric, wherein the single layer of interlayer dielectric contacts the gate dielectric layer of the gate.

### Claim 17 (depends on 16)

The electronic system of claim 16, wherein the airgap spacer comprises a void having a gas disposed therein.

### Claim 18 (depends on 17)

The electronic system of claim 17, wherein the gas comprises air.

### Claim 19 (depends on 16)

The electronic system of claim 16, wherein the gate dielectric layer is disposed between the gate electrode and the microelectronic substrate.

### Claim 20 (depends on 16)

The electronic system of claim 16, wherein the gate dielectric layer comprises a conformal layer abutting the gate electrode, and wherein the exposed portion of the gate defining the airgap spacer is only an exposed portion of the gate dielectric layer.